Commit b30c6450 authored by Geliang Tang's avatar Geliang Tang Committed by Stephen Boyd

clk: keystone: fix a trivial typo

Signed-off-by: default avatarGeliang Tang <>
Signed-off-by: default avatarStephen Boyd <>
parent 61e22fff
......@@ -157,7 +157,7 @@ out:
* _of_clk_init - PLL initialisation via DT
* @node: device tree node for this clock
* @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
* pll controller, else it is in the control regsiter0(bit 11-6)
* pll controller, else it is in the control register0(bit 11-6)
static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
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