Commit aa514ce3 authored by Gerhard Sittig's avatar Gerhard Sittig Committed by Mike Turquette

clk: wrap I/O access for improved portability

the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals

wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms
Signed-off-by: default avatarGerhard Sittig <gsi@denx.de>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 29f79cb7
......@@ -104,7 +104,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int div, val;
val = readl(divider->reg) >> divider->shift;
val = clk_readl(divider->reg) >> divider->shift;
val &= div_mask(divider);
div = _get_div(divider, val);
......@@ -230,11 +230,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) << (divider->shift + 16);
} else {
val = readl(divider->reg);
val = clk_readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift);
}
val |= value << divider->shift;
writel(val, divider->reg);
clk_writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
......
......@@ -58,7 +58,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
reg = readl(gate->reg);
reg = clk_readl(gate->reg);
if (set)
reg |= BIT(gate->bit_idx);
......@@ -66,7 +66,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg &= ~BIT(gate->bit_idx);
}
writel(reg, gate->reg);
clk_writel(reg, gate->reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
......@@ -89,7 +89,7 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
reg = readl(gate->reg);
reg = clk_readl(gate->reg);
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
......
......@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
* val = 0x4 really means "bit 2, index starts at bit 0"
*/
val = readl(mux->reg) >> mux->shift;
val = clk_readl(mux->reg) >> mux->shift;
val &= mux->mask;
if (mux->table) {
......@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
val = mux->mask << (mux->shift + 16);
} else {
val = readl(mux->reg);
val = clk_readl(mux->reg);
val &= ~(mux->mask << mux->shift);
}
val |= index << mux->shift;
writel(val, mux->reg);
clk_writel(val, mux->reg);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
......
......@@ -12,6 +12,7 @@
#define __LINUX_CLK_PROVIDER_H
#include <linux/clk.h>
#include <linux/io.h>
#ifdef CONFIG_COMMON_CLK
......@@ -504,5 +505,21 @@ static inline const char *of_clk_get_parent_name(struct device_node *np,
#define of_clk_init(matches) \
{ while (0); }
#endif /* CONFIG_OF */
/*
* wrap access to peripherals in accessor routines
* for improved portability across platforms
*/
static inline u32 clk_readl(u32 __iomem *reg)
{
return readl(reg);
}
static inline void clk_writel(u32 val, u32 __iomem *reg)
{
writel(val, reg);
}
#endif /* CONFIG_COMMON_CLK */
#endif /* CLK_PROVIDER_H */
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