Commit 82ef33af authored by Shraddha Barke's avatar Shraddha Barke Committed by Greg Kroah-Hartman

Staging: olpc_dcon: Remove obsolete driver

Remove support for One Laptop Per Child organization since it is dead.
http://www.olpcnews.com/about_olpc_news/goodbye_one_laptop_per_child.htmlSigned-off-by: default avatarShraddha Barke <shraddha.6596@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 3fe9f21a
......@@ -10392,14 +10392,6 @@ L: linux-tegra@vger.kernel.org
S: Maintained
F: drivers/staging/nvec/
STAGING - OLPC SECONDARY DISPLAY CONTROLLER (DCON)
M: Jens Frederich <jfrederich@gmail.com>
M: Daniel Drake <dsd@laptop.org>
M: Jon Nettleton <jon.nettleton@gmail.com>
W: http://wiki.laptop.org/go/DCON
S: Maintained
F: drivers/staging/olpc_dcon/
STAGING - PARALLEL LCD/KEYPAD PANEL DRIVER
M: Willy Tarreau <willy@haproxy.com>
S: Odd Fixes
......
......@@ -30,8 +30,6 @@ source "drivers/staging/wlan-ng/Kconfig"
source "drivers/staging/comedi/Kconfig"
source "drivers/staging/olpc_dcon/Kconfig"
source "drivers/staging/panel/Kconfig"
source "drivers/staging/rtl8192u/Kconfig"
......
......@@ -7,7 +7,6 @@ obj-y += media/
obj-$(CONFIG_SLICOSS) += slicoss/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_COMEDI) += comedi/
obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
obj-$(CONFIG_PANEL) += panel/
obj-$(CONFIG_RTL8192U) += rtl8192u/
obj-$(CONFIG_RTL8192E) += rtl8192e/
......
config FB_OLPC_DCON
tristate "One Laptop Per Child Display CONtroller support"
depends on OLPC && FB
depends on I2C
depends on (GPIO_CS5535 || GPIO_CS5535=n)
select BACKLIGHT_CLASS_DEVICE
---help---
In order to support very low power operation, the XO laptop uses a
secondary Display CONtroller, or DCON. This secondary controller
is present in the video pipeline between the primary display
controller (integrate into the processor or chipset) and the LCD
panel. It allows the main processor/display controller to be
completely powered off while still retaining an image on the display.
This controller is only available on OLPC platforms. Unless you have
one of these platforms, you will want to say 'N'.
config FB_OLPC_DCON_1
bool "OLPC XO-1 DCON support"
depends on FB_OLPC_DCON && GPIO_CS5535
default y
---help---
Enable support for the DCON in XO-1 model laptops. The kernel
communicates with the DCON using model-specific code. If you
have an XO-1 (or if you're unsure what model you have), you should
say 'Y'.
config FB_OLPC_DCON_1_5
bool "OLPC XO-1.5 DCON support"
depends on FB_OLPC_DCON && ACPI
default y
---help---
Enable support for the DCON in XO-1.5 model laptops. The kernel
communicates with the DCON using model-specific code. If you
have an XO-1.5 (or if you're unsure what model you have), you
should say 'Y'.
olpc-dcon-objs += olpc_dcon.o
olpc-dcon-$(CONFIG_FB_OLPC_DCON_1) += olpc_dcon_xo_1.o
olpc-dcon-$(CONFIG_FB_OLPC_DCON_1_5) += olpc_dcon_xo_1_5.o
obj-$(CONFIG_FB_OLPC_DCON) += olpc-dcon.o
TODO:
- see if vx855 gpio API can be made similar enough to cs5535 so we can
share more code
- allow simultaneous XO-1 and XO-1.5 support
Please send patches to Greg Kroah-Hartman <greg@kroah.com> and
copy:
Daniel Drake <dsd@laptop.org>
Jens Frederich <jfrederich@gmail.com>
This diff is collapsed.
#ifndef OLPC_DCON_H_
#define OLPC_DCON_H_
#include <linux/notifier.h>
#include <linux/workqueue.h>
/* DCON registers */
#define DCON_REG_ID 0
#define DCON_REG_MODE 1
#define MODE_PASSTHRU (1<<0)
#define MODE_SLEEP (1<<1)
#define MODE_SLEEP_AUTO (1<<2)
#define MODE_BL_ENABLE (1<<3)
#define MODE_BLANK (1<<4)
#define MODE_CSWIZZLE (1<<5)
#define MODE_COL_AA (1<<6)
#define MODE_MONO_LUMA (1<<7)
#define MODE_SCAN_INT (1<<8)
#define MODE_CLOCKDIV (1<<9)
#define MODE_DEBUG (1<<14)
#define MODE_SELFTEST (1<<15)
#define DCON_REG_HRES 0x2
#define DCON_REG_HTOTAL 0x3
#define DCON_REG_HSYNC_WIDTH 0x4
#define DCON_REG_VRES 0x5
#define DCON_REG_VTOTAL 0x6
#define DCON_REG_VSYNC_WIDTH 0x7
#define DCON_REG_TIMEOUT 0x8
#define DCON_REG_SCAN_INT 0x9
#define DCON_REG_BRIGHT 0xa
#define DCON_REG_MEM_OPT_A 0x41
#define DCON_REG_MEM_OPT_B 0x42
/* Load Delay Locked Loop (DLL) settings for clock delay */
#define MEM_DLL_CLOCK_DELAY (1<<0)
/* Memory controller power down function */
#define MEM_POWER_DOWN (1<<8)
/* Memory controller software reset */
#define MEM_SOFT_RESET (1<<0)
/* Status values */
#define DCONSTAT_SCANINT 0
#define DCONSTAT_SCANINT_DCON 1
#define DCONSTAT_DISPLAYLOAD 2
#define DCONSTAT_MISSED 3
/* Source values */
#define DCON_SOURCE_DCON 0
#define DCON_SOURCE_CPU 1
/* Interrupt */
#define DCON_IRQ 6
struct dcon_priv {
struct i2c_client *client;
struct fb_info *fbinfo;
struct backlight_device *bl_dev;
wait_queue_head_t waitq;
struct work_struct switch_source;
struct notifier_block reboot_nb;
/* Shadow register for the DCON_REG_MODE register */
u8 disp_mode;
/* The current backlight value - this saves us some smbus traffic */
u8 bl_val;
/* Current source, initialized at probe time */
int curr_src;
/* Desired source */
int pending_src;
/* Variables used during switches */
bool switched;
ktime_t irq_time;
ktime_t load_time;
/* Current output type; true == mono, false == color */
bool mono;
bool asleep;
/* This get set while controlling fb blank state from the driver */
bool ignore_fb_events;
};
struct dcon_platform_data {
int (*init)(struct dcon_priv *);
void (*bus_stabilize_wiggle)(void);
void (*set_dconload)(int);
int (*read_status)(u8 *);
};
#include <linux/interrupt.h>
irqreturn_t dcon_interrupt(int irq, void *id);
#ifdef CONFIG_FB_OLPC_DCON_1
extern struct dcon_platform_data dcon_pdata_xo_1;
#endif
#ifdef CONFIG_FB_OLPC_DCON_1_5
extern struct dcon_platform_data dcon_pdata_xo_1_5;
#endif
#endif
/*
* Mainly by David Woodhouse, somewhat modified by Jordan Crouse
*
* Copyright © 2006-2007 Red Hat, Inc.
* Copyright © 2006-2007 Advanced Micro Devices, Inc.
* Copyright © 2009 VIA Technology, Inc.
* Copyright (c) 2010 Andres Salomon <dilinger@queued.net>
*
* This program is free software. You can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public
* License as published by the Free Software Foundation.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/cs5535.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <asm/olpc.h>
#include "olpc_dcon.h"
static int dcon_init_xo_1(struct dcon_priv *dcon)
{
unsigned char lob;
if (gpio_request(OLPC_GPIO_DCON_STAT0, "OLPC-DCON")) {
pr_err("failed to request STAT0 GPIO\n");
return -EIO;
}
if (gpio_request(OLPC_GPIO_DCON_STAT1, "OLPC-DCON")) {
pr_err("failed to request STAT1 GPIO\n");
goto err_gp_stat1;
}
if (gpio_request(OLPC_GPIO_DCON_IRQ, "OLPC-DCON")) {
pr_err("failed to request IRQ GPIO\n");
goto err_gp_irq;
}
if (gpio_request(OLPC_GPIO_DCON_LOAD, "OLPC-DCON")) {
pr_err("failed to request LOAD GPIO\n");
goto err_gp_load;
}
if (gpio_request(OLPC_GPIO_DCON_BLANK, "OLPC-DCON")) {
pr_err("failed to request BLANK GPIO\n");
goto err_gp_blank;
}
/* Turn off the event enable for GPIO7 just to be safe */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_EVENTS_ENABLE);
/*
* Determine the current state by reading the GPIO bit; earlier
* stages of the boot process have established the state.
*
* Note that we read GPIO_OUTPUT_VAL rather than GPIO_READ_BACK here;
* this is because OFW will disable input for the pin and set a value..
* READ_BACK will only contain a valid value if input is enabled and
* then a value is set. So, future readings of the pin can use
* READ_BACK, but the first one cannot. Awesome, huh?
*/
dcon->curr_src = cs5535_gpio_isset(OLPC_GPIO_DCON_LOAD, GPIO_OUTPUT_VAL)
? DCON_SOURCE_CPU
: DCON_SOURCE_DCON;
dcon->pending_src = dcon->curr_src;
/* Set the directions for the GPIO pins */
gpio_direction_input(OLPC_GPIO_DCON_STAT0);
gpio_direction_input(OLPC_GPIO_DCON_STAT1);
gpio_direction_input(OLPC_GPIO_DCON_IRQ);
gpio_direction_input(OLPC_GPIO_DCON_BLANK);
gpio_direction_output(OLPC_GPIO_DCON_LOAD,
dcon->curr_src == DCON_SOURCE_CPU);
/* Set up the interrupt mappings */
/* Set the IRQ to pair 2 */
cs5535_gpio_setup_event(OLPC_GPIO_DCON_IRQ, 2, 0);
/* Enable group 2 to trigger the DCON interrupt */
cs5535_gpio_set_irq(2, DCON_IRQ);
/* Select edge level for interrupt (in PIC) */
lob = inb(0x4d0);
lob &= ~(1 << DCON_IRQ);
outb(lob, 0x4d0);
/* Register the interrupt handler */
if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", dcon)) {
pr_err("failed to request DCON's irq\n");
goto err_req_irq;
}
/* Clear INV_EN for GPIO7 (DCONIRQ) */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_INPUT_INVERT);
/* Enable filter for GPIO12 (DCONBLANK) */
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_INPUT_FILTER);
/* Disable filter for GPIO7 */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_INPUT_FILTER);
/* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
cs5535_gpio_clear(OLPC_GPIO_DCON_IRQ, GPIO_INPUT_EVENT_COUNT);
cs5535_gpio_clear(OLPC_GPIO_DCON_BLANK, GPIO_INPUT_EVENT_COUNT);
/* Add GPIO12 to the Filter Event Pair #7 */
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_FE7_SEL);
/* Turn off negative Edge Enable for GPIO12 */
cs5535_gpio_clear(OLPC_GPIO_DCON_BLANK, GPIO_NEGATIVE_EDGE_EN);
/* Enable negative Edge Enable for GPIO7 */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_NEGATIVE_EDGE_EN);
/* Zero the filter amount for Filter Event Pair #7 */
cs5535_gpio_set(0, GPIO_FLTR7_AMOUNT);
/* Clear the negative edge status for GPIO7 and GPIO12 */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_NEGATIVE_EDGE_STS);
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_NEGATIVE_EDGE_STS);
/* FIXME: Clear the positive status as well, just to be sure */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_POSITIVE_EDGE_STS);
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_POSITIVE_EDGE_STS);
/* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_EVENTS_ENABLE);
cs5535_gpio_set(OLPC_GPIO_DCON_BLANK, GPIO_EVENTS_ENABLE);
return 0;
err_req_irq:
gpio_free(OLPC_GPIO_DCON_BLANK);
err_gp_blank:
gpio_free(OLPC_GPIO_DCON_LOAD);
err_gp_load:
gpio_free(OLPC_GPIO_DCON_IRQ);
err_gp_irq:
gpio_free(OLPC_GPIO_DCON_STAT1);
err_gp_stat1:
gpio_free(OLPC_GPIO_DCON_STAT0);
return -EIO;
}
static void dcon_wiggle_xo_1(void)
{
int x;
/*
* According to HiMax, when powering the DCON up we should hold
* SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
* state machine to reset to a (sane) initial state. Mitch Bradley
* did some testing and discovered that holding for 16 SMB_CLK cycles
* worked a lot more reliably, so that's what we do here.
*
* According to the cs5536 spec, to set GPIO14 to SMB_CLK we must
* simultaneously set AUX1 IN/OUT to GPIO14; ditto for SMB_DATA and
* GPIO15.
*/
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_VAL);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_ENABLE);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_ENABLE);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX1);
cs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX2);
cs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX2);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_INPUT_AUX1);
cs5535_gpio_clear(OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);
for (x = 0; x < 16; x++) {
udelay(5);
cs5535_gpio_clear(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
udelay(5);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
}
udelay(5);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_AUX1);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_AUX1);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_INPUT_AUX1);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_INPUT_AUX1);
}
static void dcon_set_dconload_1(int val)
{
gpio_set_value(OLPC_GPIO_DCON_LOAD, val);
}
static int dcon_read_status_xo_1(u8 *status)
{
*status = gpio_get_value(OLPC_GPIO_DCON_STAT0);
*status |= gpio_get_value(OLPC_GPIO_DCON_STAT1) << 1;
/* Clear the negative edge status for GPIO7 */
cs5535_gpio_set(OLPC_GPIO_DCON_IRQ, GPIO_NEGATIVE_EDGE_STS);
return 0;
}
struct dcon_platform_data dcon_pdata_xo_1 = {
.init = dcon_init_xo_1,
.bus_stabilize_wiggle = dcon_wiggle_xo_1,
.set_dconload = dcon_set_dconload_1,
.read_status = dcon_read_status_xo_1,
};
/*
* Copyright (c) 2009,2010 One Laptop per Child
*
* This program is free software. You can redistribute it and/or
* modify it under the terms of version 2 of the GNU General Public
* License as published by the Free Software Foundation.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <asm/olpc.h>
/* TODO: this eventually belongs in linux/vx855.h */
#define NR_VX855_GPI 14
#define NR_VX855_GPO 13
#define NR_VX855_GPIO 15
#define VX855_GPI(n) (n)
#define VX855_GPO(n) (NR_VX855_GPI + (n))
#define VX855_GPIO(n) (NR_VX855_GPI + NR_VX855_GPO + (n))
#include "olpc_dcon.h"
/* Hardware setup on the XO 1.5:
* DCONLOAD connects to VX855_GPIO1 (not SMBCK2)
* DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
* DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
* DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
* DCONIRQ connects to VX855_GPIO12
* DCONSMBDATA connects to VX855 graphics CRTSPD
* DCONSMBCLK connects to VX855 graphics CRTSPCLK
*/
#define VX855_GENL_PURPOSE_OUTPUT 0x44c /* PMIO_Rx4c-4f */
#define VX855_GPI_STATUS_CHG 0x450 /* PMIO_Rx50 */
#define VX855_GPI_SCI_SMI 0x452 /* PMIO_Rx52 */
#define BIT_GPIO12 0x40
#define PREFIX "OLPC DCON:"
static void dcon_clear_irq(void)
{
/* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
}
static int dcon_was_irq(void)
{
u_int8_t tmp;
/* irq status will appear in PMIO_Rx50[6] on gpio12 */
tmp = inb(VX855_GPI_STATUS_CHG);
return !!(tmp & BIT_GPIO12);
return 0;
}
static int dcon_init_xo_1_5(struct dcon_priv *dcon)
{
unsigned int irq;
dcon_clear_irq();
/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
/* Determine the current state of DCONLOAD, likely set by firmware */
/* GPIO1 */
dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
DCON_SOURCE_CPU : DCON_SOURCE_DCON;
dcon->pending_src = dcon->curr_src;
/* we're sharing the IRQ with ACPI */
irq = acpi_gbl_FADT.sci_interrupt;
if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {
pr_err("DCON (IRQ%d) allocation failed\n", irq);
return 1;
}
return 0;
}
static void set_i2c_line(int sda, int scl)
{
unsigned char tmp;
unsigned int port = 0x26;
/* FIXME: This directly accesses the CRT GPIO controller !!! */
outb(port, 0x3c4);
tmp = inb(0x3c5);
if (scl)
tmp |= 0x20;
else
tmp &= ~0x20;
if (sda)
tmp |= 0x10;
else
tmp &= ~0x10;
tmp |= 0x01;
outb(port, 0x3c4);
outb(tmp, 0x3c5);
}
static void dcon_wiggle_xo_1_5(void)
{
int x;
/*
* According to HiMax, when powering the DCON up we should hold
* SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
* state machine to reset to a (sane) initial state. Mitch Bradley
* did some testing and discovered that holding for 16 SMB_CLK cycles
* worked a lot more reliably, so that's what we do here.
*/
set_i2c_line(1, 1);
for (x = 0; x < 16; x++) {
udelay(5);
set_i2c_line(1, 0);
udelay(5);
set_i2c_line(1, 1);
}
udelay(5);
/* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
}
static void dcon_set_dconload_xo_1_5(int val)
{
gpio_set_value(VX855_GPIO(1), val);
}
static int dcon_read_status_xo_1_5(u8 *status)
{
if (!dcon_was_irq())
return -1;
/* i believe this is the same as "inb(0x44b) & 3" */
*status = gpio_get_value(VX855_GPI(10));
*status |= gpio_get_value(VX855_GPI(11)) << 1;
dcon_clear_irq();
return 0;
}
struct dcon_platform_data dcon_pdata_xo_1_5 = {
.init = dcon_init_xo_1_5,
.bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
.set_dconload = dcon_set_dconload_xo_1_5,
.read_status = dcon_read_status_xo_1_5,
};
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