Commit 536630dd authored by Stephen Boyd's avatar Stephen Boyd

clk: mmp: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Cc: Chao Xie <chao.xie@marvell.com>
Signed-off-by: 's avatarStephen Boyd <sboyd@codeaurora.org>
parent f2d32b62
......@@ -99,23 +99,19 @@ void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
return;
}
clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
clk_register_clkdev(clk, "clk32", NULL);
vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
26000000);
vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
clk_register_clkdev(vctcxo, "vctcxo", NULL);
clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
800000000);
clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
clk_register_clkdev(clk, "pll1", NULL);
clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
480000000);
clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
clk_register_clkdev(clk, "usb_pll", NULL);
clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
960000000);
clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
clk_register_clkdev(clk, "pll2", NULL);
clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
......
......@@ -63,11 +63,11 @@ struct mmp2_clk_unit {
};
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
{MMP2_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
{MMP2_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
{MMP2_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 800000000},
{MMP2_CLK_PLL2, "pll2", NULL, CLK_IS_ROOT, 960000000},
{MMP2_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
{MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
{MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
{MMP2_CLK_PLL1, "pll1", NULL, 0, 800000000},
{MMP2_CLK_PLL2, "pll2", NULL, 0, 960000000},
{MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
};
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
......
......@@ -56,10 +56,10 @@ struct pxa168_clk_unit {
};
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
{PXA168_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
{PXA168_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
{PXA168_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
{PXA168_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
{PXA168_CLK_CLK32, "clk32", NULL, 0, 32768},
{PXA168_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
{PXA168_CLK_PLL1, "pll1", NULL, 0, 624000000},
{PXA168_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
};
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
......
......@@ -34,12 +34,12 @@ struct pxa1928_clk_unit {
};
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
{0, "clk32", NULL, CLK_IS_ROOT, 32768},
{0, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
{0, "pll1_624", NULL, CLK_IS_ROOT, 624000000},
{0, "pll5p", NULL, CLK_IS_ROOT, 832000000},
{0, "pll5", NULL, CLK_IS_ROOT, 1248000000},
{0, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
{0, "clk32", NULL, 0, 32768},
{0, "vctcxo", NULL, 0, 26000000},
{0, "pll1_624", NULL, 0, 624000000},
{0, "pll5p", NULL, 0, 832000000},
{0, "pll5", NULL, 0, 1248000000},
{0, "usb_pll", NULL, 0, 480000000},
};
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
......
......@@ -56,10 +56,10 @@ struct pxa910_clk_unit {
};
static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
{PXA910_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768},
{PXA910_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000},
{PXA910_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 624000000},
{PXA910_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000},
{PXA910_CLK_CLK32, "clk32", NULL, 0, 32768},
{PXA910_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
{PXA910_CLK_PLL1, "pll1", NULL, 0, 624000000},
{PXA910_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
};
static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
......
......@@ -92,15 +92,13 @@ void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
return;
}
clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
clk_register_clkdev(clk, "clk32", NULL);
clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
26000000);
clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
clk_register_clkdev(clk, "vctcxo", NULL);
clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
624000000);
clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
clk_register_clkdev(clk, "pll1", NULL);
clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
......
......@@ -97,15 +97,13 @@ void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
return;
}
clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
clk_register_clkdev(clk, "clk32", NULL);
clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
26000000);
clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
clk_register_clkdev(clk, "vctcxo", NULL);
clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
624000000);
clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
clk_register_clkdev(clk, "pll1", NULL);
clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
......
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