Commit 3dbde57a authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-for-v3.11-1' of...

Merge tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:

 - A large slew of improvements of the Genric pin configuration support,
   and deployment in four different platforms: Rockchip, Super-H PFC,
   ABx500 and TZ1090.  Support BIAS_BUS_HOLD, get device tree parsing
   and debugfs support into shape.

 - We also have device tree support with generic naming conventions for
   the generic pin configuration.

 - Delete the unused and confusing direct pinconf API.  Now state
   transitions is *the* way to control pins and multiplexing.

 - New drivers for Rockchip, TZ1090, and TZ1090 PDC.

 - Two pin control states related to power management are now handled in
   the device core: "sleep" and "idle", removing a lot of boilerplate
   code in drivers.  We do not yet know if this is the final word for
   pin PM, but it already make things a lot easier to handle.

 - Handle sparse GPIO ranges passing a list of disparate pins, and
   utilize these in the new BayTrail (x86 Atom SoC) driver.

 - Make the sunxi (AllWinner) driver handle external interrupts.

 - Make it possible for pinctrl-single to handle the case where several
   pins are managed by a single register, and augment it to handle sleep
   modes.

 - Cleanups and improvements for the abx500 drivers.

 - Move Sirf pin control drivers to their own directory, support
   save/restore of context and add support for the SiRFatlas6 SoC.

 - PMU muxing for the Dove pinctrl driver.

 - Finalization and support for VF610 in the i.MX6 pinctrl driver.

 - Smoothen out various Exynos rough edges.

 - Generic cleanups of various kinds.

* tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
  pinctrl: vt8500: wmt: remove redundant dev_err call in wmt_pinctrl_probe()
  pinctrl: remove bindings for pinconf options needing more thought
  pinctrl: remove slew-rate parameter from tz1090
  pinctrl: set unit for debounce time pinconfig to usec
  pinctrl: more clarifications for generic pull configs
  pinctrl: rip out the direct pinconf API
  pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver
  pinctrl-tz1090: add TZ1090 pinctrl driver
  pinctrl: samsung: Staticize drvdata_list
  pinctrl: rockchip: Add missing irq_gc_unlock() call before return error
  pinctrl: abx500: rework error path
  pinctrl: abx500: suppress hardcoded value
  pinctrl: abx500: factorize code
  pinctrl: abx500: fix abx500_gpio_get()
  pinctrl: abx500: fix abx500_pin_config_set()
  pinctrl: abx500: Add device tree support
  sh-pfc: Guard DT parsing with #ifdef CONFIG_OF
  pinctrl: add Intel BayTrail GPIO/pinctrl support
  pinctrl: fix pinconf_ops::pin_config_dbg_parse_modify kerneldoc
  pinctrl: Staticize local symbols
  ...

Conflicts:
	drivers/net/ethernet/ti/davinci_mdio.c
	drivers/pinctrl/Makefile
parents a6e6d863 2207a4e1
Freescale Vybrid VF610 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,vf610-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
a pin working on a specific function, CONFIG is the pad setting value
such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
datasheet for the valid pad config settings.
CONFIG bits definition:
PAD_CTL_SPEED_LOW (1 << 12)
PAD_CTL_SPEED_MED (2 << 12)
PAD_CTL_SPEED_HIGH (3 << 12)
PAD_CTL_SRE_FAST (1 << 11)
PAD_CTL_SRE_SLOW (0 << 11)
PAD_CTL_ODE (1 << 10)
PAD_CTL_HYS (1 << 9)
PAD_CTL_DSE_DISABLE (0 << 6)
PAD_CTL_DSE_150ohm (1 << 6)
PAD_CTL_DSE_75ohm (2 << 6)
PAD_CTL_DSE_50ohm (3 << 6)
PAD_CTL_DSE_37ohm (4 << 6)
PAD_CTL_DSE_30ohm (5 << 6)
PAD_CTL_DSE_25ohm (6 << 6)
PAD_CTL_DSE_20ohm (7 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_PKE (1 << 3)
PAD_CTL_PUE (1 << 2)
PAD_CTL_OBE_ENABLE (1 << 1)
PAD_CTL_IBE_ENABLE (1 << 0)
PAD_CTL_OBE_IBE_ENABLE (3 << 0)
Please refer to vf610-pinfunc.h in device tree source folder
for all available PIN_FUNC_ID for Vybrid VF610.
ImgTec TZ1090 PDC pin controller
Required properties:
- compatible: "img,tz1090-pdc-pinctrl"
- reg: Should contain the register physical address and length of the
SOC_GPIO_CONTROL registers in the PDC register region.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
TZ1090-PDC's pin configuration nodes act as a container for an abitrary number
of subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function. For this reason, even seemingly boolean
values are actually tristates in this binding: unspecified, off, or on.
Unspecified is represented as an absent property, and off/on are represented as
integer values 0 and 1.
Required subnode-properties:
- tz1090,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- tz1090,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below, including
which pingroups can be muxed to them.
- supported generic pinconfig properties (for further details see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- bias-disable
- bias-high-impedance
- bias-bus-hold
- bias-pull-up
- bias-pull-down
- input-schmitt-enable
- input-schmitt-disable
- drive-strength: Integer, control drive strength of pins in mA.
2: 2mA
4: 4mA
8: 8mA
12: 12mA
- low-power-enable: Flag, power-on-start weak pull-down for invalid power.
- low-power-disable: Flag, power-on-start weak pull-down disabled.
Note that many of these properties are only valid for certain specific pins
or groups. See the TZ1090 TRM for complete details regarding which groups
support which functionality. The Linux pinctrl driver may also be a useful
reference.
Valid values for pin and group names are:
pins:
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
bias-bus-hold (which can also be provided to any of the groups below to set
it for all gpio pins in that group).
gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
mux groups:
These all support function.
gpio0
pins: gpio0.
function: ir_mod_stable_out.
gpio1
pins: gpio1.
function: ir_mod_power_out.
drive groups:
These support input-schmitt-enable, input-schmitt-disable,
drive-strength, low-power-enable, and low-power-disable.
pdc
pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
ext_power.
Example:
pinctrl_pdc: pinctrl@02006500 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pdc-pinctrl";
reg = <0x02006500 0x100>;
};
Example board file extracts:
&pinctrl_pdc {
pinctrl-names = "default";
pinctrl-0 = <&syswake_default>;
syswake_default: syswakes {
syswake_cfg {
tz1090,pins = "sys_wake0",
"sys_wake1",
"sys_wake2";
pull-up;
};
};
irmod_default: irmod {
gpio0_cfg {
tz1090,pins = "gpio0";
tz1090,function = "ir_mod_stable_out";
};
gpio1_cfg {
tz1090,pins = "gpio1";
tz1090,function = "ir_mod_power_out";
};
};
};
ir: ir@02006200 {
pinctrl-names = "default";
pinctrl-0 = <&irmod_default>;
};
ImgTec TZ1090 pin controller
Required properties:
- compatible: "img,tz1090-pinctrl"
- reg: Should contain the register physical address and length of the pad
configuration registers (CR_PADS_* and CR_IF_CTL0).
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
TZ1090's pin configuration nodes act as a container for an abitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function. For this reason, even seemingly boolean
values are actually tristates in this binding: unspecified, off, or on.
Unspecified is represented as an absent property, and off/on are represented as
integer values 0 and 1.
Required subnode-properties:
- tz1090,pins : An array of strings. Each string contains the name of a pin or
group. Valid values for these names are listed below.
Optional subnode-properties:
- tz1090,function: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below, including
which pingroups can be muxed to them.
- supported generic pinconfig properties (for further details see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
- bias-disable
- bias-high-impedance
- bias-bus-hold
- bias-pull-up
- bias-pull-down
- input-schmitt-enable
- input-schmitt-disable
- drive-strength: Integer, control drive strength of pins in mA.
2: 2mA
4: 4mA
8: 8mA
12: 12mA
Note that many of these properties are only valid for certain specific pins
or groups. See the TZ1090 TRM for complete details regarding which groups
support which functionality. The Linux pinctrl driver may also be a useful
reference.
Valid values for pin and group names are:
gpio pins:
These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
bias-bus-hold (which can also be provided to any of the groups below to set
it for all pins in that group).
They also all support the some form of muxing. Any pins which are contained
in one of the mux groups (see below) can be muxed only to the functions
supported by the mux group. All other pins can be muxed to the "perip"
function which which enables them with their intended peripheral.
Different pins in the same mux group cannot be muxed to different functions,
however it is possible to mux only a subset of the pins in a mux group to a
particular function and leave the remaining pins unmuxed. This is useful if
the board connects certain pins in a group to other devices to be controlled
by GPIO, and you don't want the usual peripheral to have any control of the
pin.
ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
function: perip or those supported by pin's mux group.
other pins:
These other pins are part of various pin groups below, but can't be
controlled as GPIOs. They do however support bias-high-impediance,
bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
to any of the groups below to set it for all pins in that group).
clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
bias-high-impediance: supported.
bias-pull-up: supported.
bias-pull-down: supported.
bias-bus-hold: supported.
mux groups:
These all support function, and some support drive configs.
afe
pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
ant_sel1, gain0, gain1, gain2, gain3, gain4,
gain5, gain6, gain7.
function: afe, ts_out_0.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
drive-strength: supported.
pdm_d
pins: pdm_d.
function: pdm_dac, usb_vbus.
sdh
pins: sdh_cd, sdh_wp, sdh_clk_in.
function: sdh, sdio.
sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
sdio_d3.
function: sdio, sdh.
spi1_cs2
pins: spi1_cs2.
function: spi1_cs2, usb_vbus.
tft
pins: tft_red0, tft_red1, tft_red2, tft_red3,
tft_red4, tft_red5, tft_red6, tft_red7,
tft_green0, tft_green1, tft_green2, tft_green3,
tft_green4, tft_green5, tft_green6, tft_green7,
tft_blue0, tft_blue1, tft_blue2, tft_blue3,
tft_blue4, tft_blue5, tft_blue6, tft_blue7,
tft_vdden_gd, tft_panelclk, tft_blank_ls,
tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
tft_pwrsave.
function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
lcd_trace, phy_ringosc.
input-schmitt-enable: supported.
input-schmitt-disable: supported.
drive-strength: supported.
drive groups:
These all support input-schmitt-enable, input-schmitt-disable,
and drive-strength.
jtag
pins: tck, trst, tdi, tdo, tms.
scb1
pins: scb1_sdat, scb1_sclk.
scb2
pins: scb2_sdat, scb2_sclk.
spi0
pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
spi1
pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
uart
pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
uart1_txd, uart1_rxd.
drive_i2s
pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
drive_pdm
pins: clk_out0, pdm_b, pdm_a.
drive_scb0
pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
drive_sdio
pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
sdh_wp, sdh_cd, sdh_clk_in.
convenience groups:
These are just convenient groupings of pins and don't support any drive
configs.
uart0
pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
uart1
pins: uart1_rxd, uart1_txd.
scb0
pins: scb0_sclk, scb0_sdat.
i2s
pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
i2s_lrclk_out, i2s_mclk.
Example:
pinctrl: pinctrl@02005800 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pinctrl";
reg = <0x02005800 0xe4>;
};
Example board file extract:
&pinctrl {
uart0_default: uart0 {
uart0_cfg {
tz1090,pins = "uart0_rxd",
"uart0_txd";
tz1090,function = "perip";
};
};
tft_default: tft {
tft_cfg {
tz1090,pins = "tft";
tz1090,function = "tft";
};
};
};
uart@02004b00 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_default>;
};
......@@ -10,29 +10,31 @@ Required properties:
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
Note: pmu* also allows for Power Management functions listed below
name pins functions
================================================================================
mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
uart1(rts)
uart1(rts), pmu*
mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
uart1(cts), lcd-spi(cs1)
mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
mpp8 8 gpio, pmu, watchdog(rstout)
mpp9 9 gpio, pmu, pex1(clkreq)
mpp10 10 gpio, pmu, ssp(sclk)
uart1(cts), lcd-spi(cs1), pmu*
mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
mpp8 8 gpio, pmu, watchdog(rstout), pmu*
mpp9 9 gpio, pmu, pex1(clkreq), pmu*
mpp10 10 gpio, pmu, ssp(sclk), pmu*
mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
sdio1(ledctrl), pex0(clkreq)
mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
sdio1(ledctrl), pex0(clkreq), pmu*
mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
sata(act), pmu*
mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
ssp(extclk)
mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
ssp(extclk), pmu*
mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
ac97-1(sysclko)
......@@ -57,6 +59,21 @@ mpp_nand 64-71 gpo, nand
audio0 - i2s, ac97
twsi - none, opt1, opt2, opt3
Power Management functions (pmu*):
pmu-nc Pin not driven by any PM function
pmu-low Pin driven low (0)
pmu-high Pin driven high (1)
pmic(sdi) Pin is used for PMIC SDI
cpu-pwr-down Pin is used for CPU_PWRDWN
standby-pwr-down Pin is used for STBY_PWRDWN
core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
bat-fault Pin is used for BATTERY_FAULT
ext0-wakeup Pin is used for EXT0_WU
ext1-wakeup Pin is used for EXT0_WU
ext2-wakeup Pin is used for EXT0_WU
pmu-blink Pin is used for blink function
Notes:
* group "mpp_audio1" allows the following functions and gpio pins:
- gpio : gpio on pins 52-57
......
......@@ -126,3 +126,51 @@ device; they may be grandchildren, for example. Whether this is legal, and
whether there is any interaction between the child and intermediate parent
nodes, is again defined entirely by the binding for the individual pin
controller device.
== Using generic pinconfig options ==
Generic pinconfig parameters can be used by defining a separate node containing
the applicable parameters (and optional values), like:
pcfg_pull_up: pcfg_pull_up {
bias-pull-up;
drive-strength = <20>;
};
This node should then be referenced in the appropriate pinctrl node as a phandle
and parsed in the driver using the pinconf_generic_parse_dt_config function.
Supported configuration parameters are:
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
bias-pull-up - pull up the pin
bias-pull-down - pull down the pin
bias-pull-pin-default - use pin-default pull state
drive-push-pull - drive actively high and low
drive-open-drain - drive with open drain
drive-open-source - drive with open source
drive-strength - sink or source at most X mA
input-schmitt-enable - enable schmitt-trigger mode
input-schmitt-disable - disable schmitt-trigger mode
input-debounce - debounce mode with debound time X
low-power-enable - enable low power mode
low-power-disable - disable low power mode
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
Arguments for parameters:
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.
- drive-strength takes as argument the target strength in mA.
- input-debounce takes the debounce time in usec as argument
or 0 to disable debouncing
All parameters not listed here, do not take an argument.
More in-depth documentation on these parameters can be found in
<include/linux/pinctrl/pinconfig-generic.h>
......@@ -18,7 +18,8 @@ Optional properties:
pin functions is ignored
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin
more than one pin, for which "pinctrl-single,function-mask" property specifies
position mask of pin.
- pinctrl-single,drive-strength : array of value that are used to configure
drive strength in the pinmux register. They're value of drive strength
......
* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
Pin Control
-----------
Required Properties:
- compatible: should be one of the following.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
controller hardware module.
Optional properties:
- #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
otherwise. Should be 3.
The PFC node also acts as a container for pin configuration nodes. Please refer
to pinctrl-bindings.txt in this directory for the definition of the term "pin
configuration node" and for the common pinctrl bindings used by client devices.
Each pin configuration node represents a desired configuration for a pin, a
pin group, or a list of pins or pin groups. The configuration can include the
function to select on those pin(s) and pin configuration parameters (such as
pull-up and pull-down).
Pin configuration nodes contain pin configuration properties, either directly
or grouped in child subnodes. Both pin muxing and configuration parameters can
be grouped in that way and referenced as a single pin configuration node by
client devices.
A configuration node or subnode must reference at least one pin (through the
pins or pin groups properties) and contain at least a function or one
configuration parameter. When the function is present only pin groups can be
used to reference pins.
All pin configuration nodes and subnodes names are ignored. All of those nodes
are parsed through phandles and processed purely based on their content.
Pin Configuration Node Properties:
- renesas,pins : An array of strings, each string containing the name of a pin.
- renesas,groups : An array of strings, each string containing the name of a pin
group.
- renesas,function: A string containing the name of the function to mux to the
pin group(s) specified by the renesas,groups property
Valid values for pin, group and function names can be found in the group and
function arrays of the PFC data file corresponding to the SoC
(drivers/pinctrl/sh-pfc/pfc-*.c)
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
bias-disable, bias-pull-up and bias-pull-down.
GPIO
----
On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
node.
Required Properties:
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
The syntax of the gpio specifier used by client nodes should be the following
with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[flags]>
On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
for documentation of the GPIO device tree bindings on those platforms.
Examples
--------
Example 1: SH73A0 (SH-Mobile AG5) pin controller node
pfc: pfc@e6050000 {
compatible = "renesas,pfc-sh73a0";
reg = <0xe6050000 0x8000>,
<0xe605801c 0x1c>;
gpio-controller;
#gpio-cells = <2>;
};
Example 2: A GPIO LED node that references a GPIO
#include <dt-bindings/gpio/gpio.h>
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
};
};
Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
for the MMCIF and SCIFA4 devices
&pfc {
pinctrl-0 = <&scifa4_pins>;
pinctrl-names = "default";
mmcif_pins: mmcif {
mux {
renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
renesas,function = "mmc0";
};
cfg {
renesas,groups = "mmc0_data8_0";
renesas,pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: scifa4 {
renesas,groups = "scifa4_data", "scifa4_ctrl";
renesas,function = "scifa4";
};
};
Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
&mmcif {
pinctrl-0 = <&mmcif_pins>;
pinctrl-names = "default";
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
status = "okay";
};
* Rockchip Pinmux Controller
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
4 muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The Rockchip pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and
config of the pins in that group. The 'pins' selects the function mode(also
named pin mode) this pin can work on and the 'config' configures various pad
settings such as pull-up, etc.
The pins are grouped into up to 5 individual pin banks which need to be
defined as gpio sub-nodes of the pinmux controller.