Commit 270717a8 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle

MIPS: Alchemy: unify CPU model constants.

This patch removes the various CPU_AU1??? model constants in favor of
a single CPU_ALCHEMY one.

All currently existing Alchemy models are identical in terms of cpu
core and cache size/organization.  The parts of the mips kernel which
need to know the exact CPU revision extract it from the c0_prid register
already; and finally nothing else in-tree depends on those any more.

Should a new variant with slightly different "company options" and/or
"processor revision" bits in c0_prid appear, it will be supported
immediately (minus an exact model string in cpuinfo).
Signed-off-by: default avatarManuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 76544504
......@@ -209,8 +209,7 @@ enum cpu_type_enum {
* MIPS32 class processors
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
/*
* MIPS64 class processors
......
......@@ -183,13 +183,7 @@ void __init check_wait(void)
case CPU_TX49XX:
cpu_wait = r4k_wait_irqoff;
break;
case CPU_AU1000:
case CPU_AU1100:
case CPU_AU1500:
case CPU_AU1550:
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
case CPU_ALCHEMY:
cpu_wait = au1k_wait;
break;
case CPU_20KC:
......@@ -783,37 +777,30 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & 0xff00) {
case PRID_IMP_AU1_REV1:
case PRID_IMP_AU1_REV2:
c->cputype = CPU_ALCHEMY;
switch ((c->processor_id >> 24) & 0xff) {
case 0:
c->cputype = CPU_AU1000;
__cpu_name[cpu] = "Au1000";
break;
case 1:
c->cputype = CPU_AU1500;
__cpu_name[cpu] = "Au1500";
break;
case 2:
c->cputype = CPU_AU1100;
__cpu_name[cpu] = "Au1100";
break;
case 3:
c->cputype = CPU_AU1550;
__cpu_name[cpu] = "Au1550";
break;
case 4:
c->cputype = CPU_AU1200;
__cpu_name[cpu] = "Au1200";
if ((c->processor_id & 0xff) == 2) {
c->cputype = CPU_AU1250;
if ((c->processor_id & 0xff) == 2)
__cpu_name[cpu] = "Au1250";
}
break;
case 5:
c->cputype = CPU_AU1210;
__cpu_name[cpu] = "Au1210";
break;
default:
panic("Unknown Au Core!");
__cpu_name[cpu] = "Au1xxx";
break;
}
break;
......
......@@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
c->icache.flags |= MIPS_CACHE_VTAG;
break;
case CPU_AU1000:
case CPU_AU1500:
case CPU_AU1100:
case CPU_AU1550:
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
case CPU_ALCHEMY:
c->icache.flags |= MIPS_CACHE_IC_F_DC;
break;
}
......@@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void)
/*
* Au1100 errata actually keeps silence about this bit, so we set it
* just in case for those revisions that require it to be set according
* to arch/mips/au1000/common/cputable.c
* to the (now gone) cpu table.
*/
case 0x02030200: /* Au1100 AB */
case 0x02030201: /* Au1100 BA */
......@@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
break;
/*
* We need to catch the early Alchemy SOCs with
* the write-only co_config.od bit and set it back to one...
* the write-only co_config.od bit and set it back to one on:
* Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
*/
case CPU_AU1000: /* rev. DA, HA, HB */
case CPU_AU1100: /* rev. AB, BA, BC ?? */
case CPU_AU1500: /* rev. AB */
case CPU_ALCHEMY:
au1x00_fixup_config_od();
break;
......
......@@ -292,13 +292,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R4300:
case CPU_5KC:
case CPU_TX49XX:
case CPU_AU1000:
case CPU_AU1100:
case CPU_AU1500:
case CPU_AU1550:
case CPU_AU1200:
case CPU_AU1210:
case CPU_AU1250:
case CPU_ALCHEMY:
case CPU_PR4450:
uasm_i_nop(p);
tlbw(p);
......
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