Commit 1ec770d9 authored by Chao Xie's avatar Chao Xie Committed by Michael Turquette

clk: mmp: add mmp2 DT support for clock driver

It adds the DT support for mmp2 clock subsystem.
Signed-off-by: 's avatarChao Xie <chao.xie@marvell.com>
Acked-by: 's avatarHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: 's avatarMichael Turquette <mturquette@linaro.org>
parent 2bc61da9
* Marvell MMP2 Clock Controller
The MMP2 clock subsystem generates and supplies clock to various
controllers within the MMP2 SoC.
Required Properties:
- compatible: should be one of the following.
- "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
- reg: physical base address of the clock subsystem and length of memory mapped
region. There are 3 places in SOC has clock control logic:
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
......@@ -7,6 +7,7 @@ obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
obj-$(CONFIG_RESET_CONTROLLER) += reset.o
obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o
obj-$(CONFIG_MACH_MMP2_DT) += clk-of-mmp2.o
obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
......
This diff is collapsed.
#ifndef __DTS_MARVELL_MMP2_CLOCK_H
#define __DTS_MARVELL_MMP2_CLOCK_H
/* fixed clocks and plls */
#define MMP2_CLK_CLK32 1
#define MMP2_CLK_VCTCXO 2
#define MMP2_CLK_PLL1 3
#define MMP2_CLK_PLL1_2 8
#define MMP2_CLK_PLL1_4 9
#define MMP2_CLK_PLL1_8 10
#define MMP2_CLK_PLL1_16 11
#define MMP2_CLK_PLL1_3 12
#define MMP2_CLK_PLL1_6 13
#define MMP2_CLK_PLL1_12 14
#define MMP2_CLK_PLL1_20 15
#define MMP2_CLK_PLL2 16
#define MMP2_CLK_PLL2_2 17
#define MMP2_CLK_PLL2_4 18
#define MMP2_CLK_PLL2_8 19
#define MMP2_CLK_PLL2_16 20
#define MMP2_CLK_PLL2_3 21
#define MMP2_CLK_PLL2_6 22
#define MMP2_CLK_PLL2_12 23
#define MMP2_CLK_VCTCXO_2 24
#define MMP2_CLK_VCTCXO_4 25
#define MMP2_CLK_UART_PLL 26
#define MMP2_CLK_USB_PLL 27
/* apb periphrals */
#define MMP2_CLK_TWSI0 60
#define MMP2_CLK_TWSI1 61
#define MMP2_CLK_TWSI2 62
#define MMP2_CLK_TWSI3 63
#define MMP2_CLK_TWSI4 64
#define MMP2_CLK_TWSI5 65
#define MMP2_CLK_GPIO 66
#define MMP2_CLK_KPC 67
#define MMP2_CLK_RTC 68
#define MMP2_CLK_PWM0 69
#define MMP2_CLK_PWM1 70
#define MMP2_CLK_PWM2 71
#define MMP2_CLK_PWM3 72
#define MMP2_CLK_UART0 73
#define MMP2_CLK_UART1 74
#define MMP2_CLK_UART2 75
#define MMP2_CLK_UART3 76
#define MMP2_CLK_SSP0 77
#define MMP2_CLK_SSP1 78
#define MMP2_CLK_SSP2 79
#define MMP2_CLK_SSP3 80
/* axi periphrals */
#define MMP2_CLK_SDH0 101
#define MMP2_CLK_SDH1 102
#define MMP2_CLK_SDH2 103
#define MMP2_CLK_SDH3 104
#define MMP2_CLK_USB 105
#define MMP2_CLK_DISP0 106
#define MMP2_CLK_DISP0_MUX 107
#define MMP2_CLK_DISP0_SPHY 108
#define MMP2_CLK_DISP1 109
#define MMP2_CLK_DISP1_MUX 110
#define MMP2_CLK_CCIC_ARBITER 111
#define MMP2_CLK_CCIC0 112
#define MMP2_CLK_CCIC0_MIX 113
#define MMP2_CLK_CCIC0_PHY 114
#define MMP2_CLK_CCIC0_SPHY 115
#define MMP2_CLK_CCIC1 116
#define MMP2_CLK_CCIC1_MIX 117
#define MMP2_CLK_CCIC1_PHY 118
#define MMP2_CLK_CCIC1_SPHY 119
#define MMP2_NR_CLKS 200
#endif
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