ide: use PIO/MMIO operations directly where possible (v2)

This results in smaller/faster/simpler code and allows future optimizations.
Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}.

v2:
* updated for scc_pata
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
parent 7569e8dc
...@@ -81,8 +81,6 @@ static inline void hwif_setup(ide_hwif_t *hwif) ...@@ -81,8 +81,6 @@ static inline void hwif_setup(ide_hwif_t *hwif)
hwif->OUTSW = mm_outsw; hwif->OUTSW = mm_outsw;
hwif->INW = mm_inw; hwif->INW = mm_inw;
hwif->INSW = mm_insw; hwif->INSW = mm_insw;
hwif->OUTL = NULL;
hwif->INL = NULL;
hwif->OUTSL = NULL; hwif->OUTSL = NULL;
hwif->INSL = NULL; hwif->INSL = NULL;
} }
......
...@@ -565,7 +565,10 @@ int ide_dma_setup(ide_drive_t *drive) ...@@ -565,7 +565,10 @@ int ide_dma_setup(ide_drive_t *drive)
} }
/* PRD table */ /* PRD table */
hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable); if (hwif->mmio == 2)
writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable);
else
outl(hwif->dmatable_dma, hwif->dma_prdtable);
/* specify r/w */ /* specify r/w */
hwif->OUTB(reading, hwif->dma_command); hwif->OUTB(reading, hwif->dma_command);
......
...@@ -49,11 +49,6 @@ static void ide_insw (unsigned long port, void *addr, u32 count) ...@@ -49,11 +49,6 @@ static void ide_insw (unsigned long port, void *addr, u32 count)
insw(port, addr, count); insw(port, addr, count);
} }
static u32 ide_inl (unsigned long port)
{
return (u32) inl(port);
}
static void ide_insl (unsigned long port, void *addr, u32 count) static void ide_insl (unsigned long port, void *addr, u32 count)
{ {
insl(port, addr, count); insl(port, addr, count);
...@@ -79,11 +74,6 @@ static void ide_outsw (unsigned long port, void *addr, u32 count) ...@@ -79,11 +74,6 @@ static void ide_outsw (unsigned long port, void *addr, u32 count)
outsw(port, addr, count); outsw(port, addr, count);
} }
static void ide_outl (u32 val, unsigned long port)
{
outl(val, port);
}
static void ide_outsl (unsigned long port, void *addr, u32 count) static void ide_outsl (unsigned long port, void *addr, u32 count)
{ {
outsl(port, addr, count); outsl(port, addr, count);
...@@ -94,12 +84,10 @@ void default_hwif_iops (ide_hwif_t *hwif) ...@@ -94,12 +84,10 @@ void default_hwif_iops (ide_hwif_t *hwif)
hwif->OUTB = ide_outb; hwif->OUTB = ide_outb;
hwif->OUTBSYNC = ide_outbsync; hwif->OUTBSYNC = ide_outbsync;
hwif->OUTW = ide_outw; hwif->OUTW = ide_outw;
hwif->OUTL = ide_outl;
hwif->OUTSW = ide_outsw; hwif->OUTSW = ide_outsw;
hwif->OUTSL = ide_outsl; hwif->OUTSL = ide_outsl;
hwif->INB = ide_inb; hwif->INB = ide_inb;
hwif->INW = ide_inw; hwif->INW = ide_inw;
hwif->INL = ide_inl;
hwif->INSW = ide_insw; hwif->INSW = ide_insw;
hwif->INSL = ide_insl; hwif->INSL = ide_insl;
} }
...@@ -123,11 +111,6 @@ static void ide_mm_insw (unsigned long port, void *addr, u32 count) ...@@ -123,11 +111,6 @@ static void ide_mm_insw (unsigned long port, void *addr, u32 count)
__ide_mm_insw((void __iomem *) port, addr, count); __ide_mm_insw((void __iomem *) port, addr, count);
} }
static u32 ide_mm_inl (unsigned long port)
{
return (u32) readl((void __iomem *) port);
}
static void ide_mm_insl (unsigned long port, void *addr, u32 count) static void ide_mm_insl (unsigned long port, void *addr, u32 count)
{ {
__ide_mm_insl((void __iomem *) port, addr, count); __ide_mm_insl((void __iomem *) port, addr, count);
...@@ -153,11 +136,6 @@ static void ide_mm_outsw (unsigned long port, void *addr, u32 count) ...@@ -153,11 +136,6 @@ static void ide_mm_outsw (unsigned long port, void *addr, u32 count)
__ide_mm_outsw((void __iomem *) port, addr, count); __ide_mm_outsw((void __iomem *) port, addr, count);
} }
static void ide_mm_outl (u32 value, unsigned long port)
{
writel(value, (void __iomem *) port);
}
static void ide_mm_outsl (unsigned long port, void *addr, u32 count) static void ide_mm_outsl (unsigned long port, void *addr, u32 count)
{ {
__ide_mm_outsl((void __iomem *) port, addr, count); __ide_mm_outsl((void __iomem *) port, addr, count);
...@@ -170,12 +148,10 @@ void default_hwif_mmiops (ide_hwif_t *hwif) ...@@ -170,12 +148,10 @@ void default_hwif_mmiops (ide_hwif_t *hwif)
this one is controller specific! */ this one is controller specific! */
hwif->OUTBSYNC = ide_mm_outbsync; hwif->OUTBSYNC = ide_mm_outbsync;
hwif->OUTW = ide_mm_outw; hwif->OUTW = ide_mm_outw;
hwif->OUTL = ide_mm_outl;
hwif->OUTSW = ide_mm_outsw; hwif->OUTSW = ide_mm_outsw;
hwif->OUTSL = ide_mm_outsl; hwif->OUTSL = ide_mm_outsl;
hwif->INB = ide_mm_inb; hwif->INB = ide_mm_inb;
hwif->INW = ide_mm_inw; hwif->INW = ide_mm_inw;
hwif->INL = ide_mm_inl;
hwif->INSW = ide_mm_insw; hwif->INSW = ide_mm_insw;
hwif->INSL = ide_mm_insl; hwif->INSL = ide_mm_insl;
} }
......
...@@ -518,13 +518,11 @@ static void ide_hwif_restore(ide_hwif_t *hwif, ide_hwif_t *tmp_hwif) ...@@ -518,13 +518,11 @@ static void ide_hwif_restore(ide_hwif_t *hwif, ide_hwif_t *tmp_hwif)
hwif->OUTB = tmp_hwif->OUTB; hwif->OUTB = tmp_hwif->OUTB;
hwif->OUTBSYNC = tmp_hwif->OUTBSYNC; hwif->OUTBSYNC = tmp_hwif->OUTBSYNC;
hwif->OUTW = tmp_hwif->OUTW; hwif->OUTW = tmp_hwif->OUTW;
hwif->OUTL = tmp_hwif->OUTL;
hwif->OUTSW = tmp_hwif->OUTSW; hwif->OUTSW = tmp_hwif->OUTSW;
hwif->OUTSL = tmp_hwif->OUTSL; hwif->OUTSL = tmp_hwif->OUTSL;
hwif->INB = tmp_hwif->INB; hwif->INB = tmp_hwif->INB;
hwif->INW = tmp_hwif->INW; hwif->INW = tmp_hwif->INW;
hwif->INL = tmp_hwif->INL;
hwif->INSW = tmp_hwif->INSW; hwif->INSW = tmp_hwif->INSW;
hwif->INSL = tmp_hwif->INSL; hwif->INSL = tmp_hwif->INSL;
......
...@@ -143,16 +143,16 @@ static void ht6560b_selectproc (ide_drive_t *drive) ...@@ -143,16 +143,16 @@ static void ht6560b_selectproc (ide_drive_t *drive)
current_timing = timing; current_timing = timing;
if (drive->media != ide_disk || !drive->present) if (drive->media != ide_disk || !drive->present)
select |= HT_PREFETCH_MODE; select |= HT_PREFETCH_MODE;
(void) HWIF(drive)->INB(HT_CONFIG_PORT); (void)inb(HT_CONFIG_PORT);
(void) HWIF(drive)->INB(HT_CONFIG_PORT); (void)inb(HT_CONFIG_PORT);
(void) HWIF(drive)->INB(HT_CONFIG_PORT); (void)inb(HT_CONFIG_PORT);
(void) HWIF(drive)->INB(HT_CONFIG_PORT); (void)inb(HT_CONFIG_PORT);
HWIF(drive)->OUTB(select, HT_CONFIG_PORT); outb(select, HT_CONFIG_PORT);
/* /*
* Set timing for this drive: * Set timing for this drive:
*/ */
HWIF(drive)->OUTB(timing, IDE_SELECT_REG); outb(timing, IDE_SELECT_REG);
(void) HWIF(drive)->INB(IDE_STATUS_REG); (void)inb(IDE_STATUS_REG);
#ifdef DEBUG #ifdef DEBUG
printk("ht6560b: %s: select=%#x timing=%#x\n", printk("ht6560b: %s: select=%#x timing=%#x\n",
drive->name, select, timing); drive->name, select, timing);
......
...@@ -94,9 +94,9 @@ static u8 aec62xx_ratemask (ide_drive_t *drive) ...@@ -94,9 +94,9 @@ static u8 aec62xx_ratemask (ide_drive_t *drive)
switch(hwif->pci_dev->device) { switch(hwif->pci_dev->device) {
case PCI_DEVICE_ID_ARTOP_ATP865: case PCI_DEVICE_ID_ARTOP_ATP865:
case PCI_DEVICE_ID_ARTOP_ATP865R: case PCI_DEVICE_ID_ARTOP_ATP865R:
mode = (hwif->INB(((hwif->channel) ? mode = (inb(hwif->channel ?
hwif->mate->dma_status : hwif->mate->dma_status :
hwif->dma_status)) & 0x10) ? 4 : 3; hwif->dma_status) & 0x10) ? 4 : 3;
break; break;
case PCI_DEVICE_ID_ARTOP_ATP860: case PCI_DEVICE_ID_ARTOP_ATP860:
case PCI_DEVICE_ID_ARTOP_ATP860R: case PCI_DEVICE_ID_ARTOP_ATP860R:
......
...@@ -852,8 +852,8 @@ static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase) ...@@ -852,8 +852,8 @@ static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
{ {
if (m5229_revision < 0x20) if (m5229_revision < 0x20)
return; return;
if (!(hwif->channel)) if (!hwif->channel)
hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2); outb(inb(dmabase + 2) & 0x60, dmabase + 2);
ide_setup_dma(hwif, dmabase, 8); ide_setup_dma(hwif, dmabase, 8);
} }
......
...@@ -507,13 +507,13 @@ static int cmd64x_ide_dma_end (ide_drive_t *drive) ...@@ -507,13 +507,13 @@ static int cmd64x_ide_dma_end (ide_drive_t *drive)
drive->waiting_for_dma = 0; drive->waiting_for_dma = 0;
/* read DMA command state */ /* read DMA command state */
dma_cmd = hwif->INB(hwif->dma_command); dma_cmd = inb(hwif->dma_command);
/* stop DMA */ /* stop DMA */
hwif->OUTB((dma_cmd & ~1), hwif->dma_command); outb(dma_cmd & ~1, hwif->dma_command);
/* get DMA status */ /* get DMA status */
dma_stat = hwif->INB(hwif->dma_status); dma_stat = inb(hwif->dma_status);
/* clear the INTR & ERROR bits */ /* clear the INTR & ERROR bits */
hwif->OUTB(dma_stat|6, hwif->dma_status); outb(dma_stat | 6, hwif->dma_status);
if (cmd64x_alt_dma_status(dev)) { if (cmd64x_alt_dma_status(dev)) {
u8 dma_intr = 0; u8 dma_intr = 0;
u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 : u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
...@@ -535,7 +535,7 @@ static int cmd64x_ide_dma_test_irq (ide_drive_t *drive) ...@@ -535,7 +535,7 @@ static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
struct pci_dev *dev = hwif->pci_dev; struct pci_dev *dev = hwif->pci_dev;
u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 : u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
MRDMODE_INTR_CH0; MRDMODE_INTR_CH0;
u8 dma_stat = hwif->INB(hwif->dma_status); u8 dma_stat = inb(hwif->dma_status);
(void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat); (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
#ifdef DEBUG #ifdef DEBUG
...@@ -565,13 +565,13 @@ static int cmd646_1_ide_dma_end (ide_drive_t *drive) ...@@ -565,13 +565,13 @@ static int cmd646_1_ide_dma_end (ide_drive_t *drive)
drive->waiting_for_dma = 0; drive->waiting_for_dma = 0;
/* get DMA status */ /* get DMA status */
dma_stat = hwif->INB(hwif->dma_status); dma_stat = inb(hwif->dma_status);
/* read DMA command state */ /* read DMA command state */
dma_cmd = hwif->INB(hwif->dma_command); dma_cmd = inb(hwif->dma_command);
/* stop DMA */ /* stop DMA */
hwif->OUTB((dma_cmd & ~1), hwif->dma_command); outb(dma_cmd & ~1, hwif->dma_command);
/* clear the INTR & ERROR bits */ /* clear the INTR & ERROR bits */
hwif->OUTB(dma_stat|6, hwif->dma_status); outb(dma_stat | 6, hwif->dma_status);
/* and free any DMA resources */ /* and free any DMA resources */
ide_destroy_dmatable(drive); ide_destroy_dmatable(drive);
/* verify good DMA status */ /* verify good DMA status */
......
...@@ -81,8 +81,8 @@ static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autot ...@@ -81,8 +81,8 @@ static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autot
pio = ide_get_best_pio_mode(drive, pio, 4, NULL); pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
if (!cs5530_set_xfer_mode(drive, modes[pio])) { if (!cs5530_set_xfer_mode(drive, modes[pio])) {
format = (hwif->INL(basereg+4) >> 31) & 1; format = (inl(basereg + 4) >> 31) & 1;
hwif->OUTL(cs5530_pio_timings[format][pio], outl(cs5530_pio_timings[format][pio],
basereg+(drive->select.b.unit<<3)); basereg+(drive->select.b.unit<<3));
} }
} }
...@@ -183,17 +183,17 @@ static int cs5530_config_dma (ide_drive_t *drive) ...@@ -183,17 +183,17 @@ static int cs5530_config_dma (ide_drive_t *drive)
break; break;
} }
basereg = CS5530_BASEREG(hwif); basereg = CS5530_BASEREG(hwif);
reg = hwif->INL(basereg+4); /* get drive0 config register */ reg = inl(basereg + 4); /* get drive0 config register */
timings |= reg & 0x80000000; /* preserve PIO format bit */ timings |= reg & 0x80000000; /* preserve PIO format bit */
if (unit == 0) { /* are we configuring drive0? */ if (unit == 0) { /* are we configuring drive0? */
hwif->OUTL(timings, basereg+4); /* write drive0 config register */ outl(timings, basereg + 4); /* write drive0 config register */
} else { } else {
if (timings & 0x00100000) if (timings & 0x00100000)
reg |= 0x00100000; /* enable UDMA timings for both drives */ reg |= 0x00100000; /* enable UDMA timings for both drives */
else else
reg &= ~0x00100000; /* disable UDMA timings for both drives */ reg &= ~0x00100000; /* disable UDMA timings for both drives */
hwif->OUTL(reg, basereg+4); /* write drive0 config register */ outl(reg, basereg + 4); /* write drive0 config register */
hwif->OUTL(timings, basereg+12); /* write drive1 config register */ outl(timings, basereg + 12); /* write drive1 config register */
} }
/* /*
...@@ -315,17 +315,17 @@ static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif) ...@@ -315,17 +315,17 @@ static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
hwif->tuneproc = &cs5530_tuneproc; hwif->tuneproc = &cs5530_tuneproc;
basereg = CS5530_BASEREG(hwif); basereg = CS5530_BASEREG(hwif);
d0_timings = hwif->INL(basereg+0); d0_timings = inl(basereg + 0);
if (CS5530_BAD_PIO(d0_timings)) { if (CS5530_BAD_PIO(d0_timings)) {
/* PIO timings not initialized? */ /* PIO timings not initialized? */
hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0); outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
if (!hwif->drives[0].autotune) if (!hwif->drives[0].autotune)
hwif->drives[0].autotune = 1; hwif->drives[0].autotune = 1;
/* needs autotuning later */ /* needs autotuning later */
} }
if (CS5530_BAD_PIO(hwif->INL(basereg+8))) { if (CS5530_BAD_PIO(inl(basereg + 8))) {
/* PIO timings not initialized? */ /* PIO timings not initialized? */
hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8); outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
if (!hwif->drives[1].autotune) if (!hwif->drives[1].autotune)
hwif->drives[1].autotune = 1; hwif->drives[1].autotune = 1;
/* needs autotuning later */ /* needs autotuning later */
......
...@@ -197,8 +197,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single) ...@@ -197,8 +197,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
#if CY82C693_DEBUG_LOGS #if CY82C693_DEBUG_LOGS
/* for debug let's show the previous values */ /* for debug let's show the previous values */
HWIF(drive)->OUTB(index, CY82_INDEX_PORT); outb(index, CY82_INDEX_PORT);
data = HWIF(drive)->INB(CY82_DATA_PORT); data = inb(CY82_DATA_PORT);
printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
drive->name, HWIF(drive)->channel, drive->select.b.unit, drive->name, HWIF(drive)->channel, drive->select.b.unit,
...@@ -207,8 +207,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single) ...@@ -207,8 +207,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
data = (u8)mode|(u8)(single<<2); data = (u8)mode|(u8)(single<<2);
HWIF(drive)->OUTB(index, CY82_INDEX_PORT); outb(index, CY82_INDEX_PORT);
HWIF(drive)->OUTB(data, CY82_DATA_PORT); outb(data, CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO #if CY82C693_DEBUG_INFO
printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
...@@ -227,8 +227,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single) ...@@ -227,8 +227,8 @@ static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
*/ */
data = BUSMASTER_TIMEOUT; data = BUSMASTER_TIMEOUT;
HWIF(drive)->OUTB(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT); outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
HWIF(drive)->OUTB(data, CY82_DATA_PORT); outb(data, CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO #if CY82C693_DEBUG_INFO
printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n", printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
......
...@@ -836,7 +836,7 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive) ...@@ -836,7 +836,7 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
return 0; return 0;
} }
dma_stat = hwif->INB(hwif->dma_status); dma_stat = inb(hwif->dma_status);
/* return 1 if INTR asserted */ /* return 1 if INTR asserted */
if (dma_stat & 4) if (dma_stat & 4)
return 1; return 1;
......
...@@ -166,10 +166,10 @@ static int ns87415_ide_dma_end (ide_drive_t *drive) ...@@ -166,10 +166,10 @@ static int ns87415_ide_dma_end (ide_drive_t *drive)
/* get dma command mode */ /* get dma command mode */
dma_cmd = hwif->INB(hwif->dma_command); dma_cmd = hwif->INB(hwif->dma_command);
/* stop DMA */ /* stop DMA */
hwif->OUTB(dma_cmd & ~1, hwif->dma_command); outb(dma_cmd & ~1, hwif->dma_command);
/* from ERRATA: clear the INTR & ERROR bits */ /* from ERRATA: clear the INTR & ERROR bits */
dma_cmd = hwif->INB(hwif->dma_command); dma_cmd = hwif->INB(hwif->dma_command);
hwif->OUTB(dma_cmd|6, hwif->dma_command); outb(dma_cmd | 6, hwif->dma_command);
/* and free any DMA resources */ /* and free any DMA resources */
ide_destroy_dmatable(drive); ide_destroy_dmatable(drive);
/* verify good DMA status */ /* verify good DMA status */
...@@ -243,9 +243,9 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) ...@@ -243,9 +243,9 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
* to SELECT_DRIVE() properly during first probe_hwif(). * to SELECT_DRIVE() properly during first probe_hwif().
*/ */
timeout = 10000; timeout = 10000;
hwif->OUTB(12, hwif->io_ports[IDE_CONTROL_OFFSET]); outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
udelay(10); udelay(10);
hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]); outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
do { do {
udelay(50); udelay(50);
stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]); stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
...@@ -263,7 +263,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif) ...@@ -263,7 +263,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
if (!hwif->dma_base) if (!hwif->dma_base)
return; return;
hwif->OUTB(0x60, hwif->dma_status); outb(0x60, hwif->dma_status);
hwif->dma_setup = &ns87415_ide_dma_setup; hwif->dma_setup = &ns87415_ide_dma_setup;
hwif->ide_dma_check = &ns87415_ide_dma_check; hwif->ide_dma_check = &ns87415_ide_dma_check;
hwif->ide_dma_end = &ns87415_ide_dma_end; hwif->ide_dma_end = &ns87415_ide_dma_end;
......
...@@ -176,34 +176,35 @@ static int cmpt_clk(int time, int bus_speed) ...@@ -176,34 +176,35 @@ static int cmpt_clk(int time, int bus_speed)
return ((time*bus_speed+999)/1000); return ((time*bus_speed+999)/1000);
} }
static void write_reg(ide_hwif_t *hwif, u8 value, int reg)
/* Write value to register reg, base of register /* Write value to register reg, base of register
* is at reg_base (0x1f0 primary, 0x170 secondary, * is at reg_base (0x1f0 primary, 0x170 secondary,
* if not changed by PCI configuration). * if not changed by PCI configuration).
* This is from setupvic.exe program. * This is from setupvic.exe program.
*/ */
static void write_reg(u8 value, int reg)
{ {
hwif->INW(reg_base+1); inw(reg_base + 1);
hwif->INW(reg_base+1); inw(reg_base + 1);
hwif->OUTB(3, reg_base+2); outb(3, reg_base + 2);
hwif->OUTB(value, reg_base+reg); outb(value, reg_base + reg);
hwif->OUTB(0x83, reg_base+2); outb(0x83, reg_base + 2);
} }
static u8 read_reg(ide_hwif_t *hwif, int reg)
/* Read value from register reg, base of register /* Read value from register reg, base of register
* is at reg_base (0x1f0 primary, 0x170 secondary, * is at reg_base (0x1f0 primary, 0x170 secondary,
* if not changed by PCI configuration). * if not changed by PCI configuration).
* This is from setupvic.exe program. * This is from setupvic.exe program.
*/ */
static u8 read_reg(int reg)
{ {
u8 ret = 0; u8 ret = 0;
hwif->INW(reg_base+1); inw(reg_base + 1);
hwif->INW(reg_base+1); inw(reg_base + 1);
hwif->OUTB(3, reg_base+2); outb(3, reg_base + 2);
ret = hwif->INB(reg_base+reg); ret = inb(reg_base + reg);
hwif->OUTB(0x83, reg_base+2); outb(0x83, reg_base + 2);
return ret; return ret;
} }
...@@ -286,39 +287,39 @@ static void opti621_tune_drive (ide_drive_t *drive, u8 pio) ...@@ -286,39 +287,39 @@ static void opti621_tune_drive (ide_drive_t *drive, u8 pio)
reg_base = hwif->io_ports[IDE_DATA_OFFSET]; reg_base = hwif->io_ports[IDE_DATA_OFFSET];
/* allow Register-B */ /* allow Register-B */
hwif->OUTB(0xc0, reg_base+CNTRL_REG); outb(0xc0, reg_base + CNTRL_REG);
/* hmm, setupvic.exe does this ;-) */ /* hmm, setupvic.exe does this ;-) */
hwif->OUTB(0xff, reg_base+5); outb(0xff, reg_base + 5);
/* if reads 0xff, adapter not exist? */ /* if reads 0xff, adapter not exist? */
(void) hwif->INB(reg_base+CNTRL_REG); (void)inb(reg_base + CNTRL_REG);
/* if reads 0xc0, no interface exist? */ /* if reads 0xc0, no interface exist? */
read_reg(hwif, CNTRL_REG); read_reg(CNTRL_REG);
/* read version, probably 0 */ /* read version, probably 0 */
read_reg(hwif, STRAP_REG); read_reg(STRAP_REG);
/* program primary drive */ /* program primary drive */
/* select Index-0 for Register-A */ /* select Index-0 for Register-A */
write_reg(hwif, 0, MISC_REG); write_reg(0, MISC_REG);
/* set read cycle timings */ /* set read cycle timings */
write_reg(hwif, cycle1, READ_REG); write_reg(cycle1, READ_REG);
/* set write cycle timings */ /* set write cycle timings */
write_reg(hwif, cycle1, WRITE_REG); write_reg(cycle1, WRITE_REG);
/* program secondary drive */ /* program secondary drive */
/* select Index-1 for Register-B */ /* select Index-1 for Register-B */
write_reg(hwif, 1, MISC_REG); write_reg(1, MISC_REG);
/* set read cycle timings */ /* set read cycle timings */
write_reg(hwif, cycle2, READ_REG); write_reg(cycle2, READ_REG);
/* set write cycle timings */ /* set write cycle timings */
write_reg(hwif, cycle2, WRITE_REG); write_reg(cycle2, WRITE_REG);
/* use Register-A for drive 0 */ /* use Register-A for drive 0 */
/* use Register-B for drive 1 */ /* use Register-B for drive 1 */
write_reg(hwif, 0x85, CNTRL_REG); write_reg(0x85, CNTRL_REG);
/* set address setup, DRDY timings, */ /* set address setup, DRDY timings, */
/* and read prefetch for both drives */ /* and read prefetch for both drives */
write_reg(hwif, misc, MISC_REG); write_reg(misc, MISC_REG);
spin_unlock_irqrestore(&ide_lock, flags); spin_unlock_irqrestore(&ide_lock, flags);
} }
......
...@@ -101,8 +101,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index) ...@@ -101,8 +101,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
{ {
u8 value; u8 value;
hwif->OUTB(index, hwif->dma_vendor1); outb(index, hwif->dma_vendor1);
value = hwif->INB(hwif->dma_vendor3); value = inb(hwif->dma_vendor3);
DBG("index[%02X] value[%02X]\n", index, value); DBG("index[%02X] value[%02X]\n", index, value);
return value; return value;
...@@ -115,8 +115,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index) ...@@ -115,8 +115,8 @@ static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
*/ */
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value) static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{ {
hwif->OUTB(index, hwif->dma_vendor1); outb(index, hwif->dma_vendor1);
hwif->OUTB(value, hwif->dma_vendor3); outb(value, hwif->dma_vendor3);
DBG("index[%02X] value[%02X]\n", index, value); DBG("index[%02X] value[%02X]\n", index, value);
} }
......
...@@ -240,17 +240,17 @@ static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif) ...@@ -240,17 +240,17 @@ static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{ {
unsigned long clock_reg = hwif->dma_master + 0x11; unsigned long clock_reg = hwif->dma_master + 0x11;
u8 clock = hwif->INB(clock_reg); u8 clock = inb(clock_reg);
hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
} }
static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{ {
unsigned long clock_reg = hwif->dma_master + 0x11; unsigned long clock_reg = hwif->dma_master + 0x11;
u8 clock = hwif->INB(clock_reg); u8 clock = inb(clock_reg);
hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
} }
static int config_chipset_for_dma (ide_drive_t *drive) static int config_chipset_for_dma (ide_drive_t *drive)
...@@ -357,14 +357,14 @@ static void pdc202xx_old_ide_dma_start(ide_drive_t *drive) ...@@ -357,14 +357,14 @@ static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
unsigned long high_16 = hwif->dma_master; unsigned long high_16 = hwif->dma_master;
unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
u32 word_count = 0; u32 word_count = 0;
u8 clock = hwif->INB(high_16 + 0x11); u8 clock = inb(high_16 + 0x11);
hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11); outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
word_count = (rq->nr_sectors << 8); word_count = (rq->nr_sectors << 8);
word_count = (rq_data_dir(rq) == READ) ? word_count = (rq_data_dir(rq) == READ) ?
word_count | 0x05000000 : word_count | 0x05000000 :
word_count | 0x06000000; word_count | 0x06000000;
hwif->OUTL(word_count, atapi_reg); outl(word_count, atapi_reg);
} }
ide_dma_start(drive); ide_dma_start(drive);
} }
...@@ -377,9 +377,9 @@ static int pdc202xx_old_ide_dma_end(ide_drive_t *drive) ...@@ -377,9 +377,9 @@ static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); unsigned long atapi_reg = high_16 +