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  • Cyrille Pitchen's avatar
    tty/serial: at91: add support to FIFOs · b5199d46
    Cyrille Pitchen authored
    
    
    Depending on the hardware, TX and RX FIFOs may be available. The RX
    FIFO can avoid receive overruns, especially when DMA transfers are
    not used to read data from the Receive Holding Register. For heavy
    system load, The CPU is likely not be able to fetch data fast enough
    from the RHR.
    
    In addition, the RX FIFO can supersede the DMA/PDC to control the RTS
    line when the Hardware Handshaking mode is enabled. Two thresholds
    are to be set for that purpose:
    - When the number of data in the RX FIFO crosses and becomes lower
      than or equal to the low threshold, the RTS line is set to low
      level: the remote peer is requested to send data.
    - When the number of data in the RX FIFO crosses and becomes greater
      than or equal to the high threshold, the RTS line is set to high
      level: the remote peer should stop sending new data.
    - low threshold <= high threshold
    Once these two thresholds are set properly, this new feature is
    enabled by setting the FIFO RTS Control bit of the FIFO Mode Register.
    
    FIFOs also introduce a new multiple data mode: the USART works either
    in multiple data mode or in single data (legacy) mode.
    
    If MODE9 bit is set into the Mode Register or if USMODE is set to
    either LIN_MASTER, LIN_SLAVE or LON_MODE, FIFOs operate in single
    data mode. Otherwise, they operate in multiple data mode.
    
    In this new multiple data mode, accesses to the Receive Holding
    Register or Transmit Holding Register slightly change.
    
    Since this driver implements neither the 9bit data feature (MODE9 bit
    set into the Mode Register) nor LIN modes, the USART works in
    multiple data mode whenever FIFOs are available and enabled. We also
    assume that data are 8bit wide.
    
    In single data mode, 32bit access CAN be used to read a single data
    from RHR or write a single data into THR.
    However in multiple data mode, a 32bit access to RHR now allows us to
    read four consecutive data from RX FIFO. Also a 32bit access to THR
    now allows to write four consecutive data into TX FIFO. So we MUST
    use 8bit access whenever only one data have to be read/written at a
    time.
    
    Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
    Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    b5199d46