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    [SPARC64]: Fix TLB context allocation with SMT style shared TLBs. · a0663a79
    David S. Miller authored
    
    
    The context allocation scheme we use depends upon there being a 1<-->1
    mapping from cpu to physical TLB for correctness.  Chips like Niagara
    break this assumption.
    
    So what we do is notify all cpus with a cross call when the context
    version number changes, and if necessary this makes them allocate
    a valid context for the address space they are running at the time.
    
    Stress tested with make -j1024, make -j2048, and make -j4096 kernel
    builds on a 32-strand, 8 core, T2000 with 16GB of ram.
    
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    a0663a79