• Lukasz Odzioba's avatar
    EDAC, sb_edac: Fix channel reporting on Knights Landing · c5b48fa7
    Lukasz Odzioba authored
    On Intel Xeon Phi Knights Landing processor family the channels of the
    memory controller have untypical arrangement - MC0 is mapped to CH3,4,5
    and MC1 is mapped to CH0,1,2. This causes the EDAC driver to report the
    channel name incorrectly.
    We missed this change earlier, so the code already contains similar
    comment, but the translation function is incorrect.
    Without this patch:
      errors in DIMM_A and DIMM_D were reported in DIMM_D
      errors in DIMM_B and DIMM_E were reported in DIMM_E
      errors in DIMM_C and DIMM_F were reported in DIMM_F
    Correct this.
    Hubert Chrzaniuk:
     - rebased to 4.8
     - comments and code cleanup
    Fixes: d0cdf900 ("sb_edac: Add Knights Landing (Xeon Phi gen 2) support")
    Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
    Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
    Cc: Hubert Chrzaniuk <hubert.chrzaniuk@intel.com>
    Cc: linux-edac <linux-edac@vger.kernel.org>
    Cc: lukasz.anaczkowski@intel.com
    Cc: lukasz.odzioba@intel.com
    Cc: mchehab@kernel.org
    Cc: <stable@vger.kernel.org> # v4.5..
    Link: http://lkml.kernel.org/r/1469231089-22837-1-git-send-email-lukasz.odzioba@intel.comSigned-off-by: default avatarLukasz Odzioba <lukasz.odzioba@intel.com>
    [ Boris: Simplify a bit by removing char mc. ]
    Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
sb_edac.c 91.1 KB