• Dinh Nguyen's avatar
    clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" · 044abbde
    Dinh Nguyen authored
    The clk-phase property is used to represent the 2 clock phase values that is
    needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
    use the syscon driver to set sdmmc_clk's phase shift that is located in the
    system manager.
    Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
    Acked-by: default avatarZhangfei Gao <zhangfei.gao@linaro.org>
    Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
    v9: none
    v8: Use degrees in the clk-phase binding property
    v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
        prepare function to the gate clk that will toggle clock phase setting.
        Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
    v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
        set the phase shift settings.
    v5: Use the "snps,dw-mshc" binding
    v4: Use the sdmmc_clk prepare function to set the phase shift settings
    v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
        loaded after the clock driver.
    v2: Use the syscon driver
clk-gate.c 6.74 KB