spi-fsl-spi.c 22.6 KB
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/*
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 * Freescale SPI controller driver.
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 *
 * Maintainer: Kumar Gala
 *
 * Copyright (C) 2006 Polycom, Inc.
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 * Copyright 2010 Freescale Semiconductor, Inc.
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 *
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 * CPM SPI and QE buffer descriptors mode support:
 * Copyright (c) 2009  MontaVista Software, Inc.
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
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 * GRLIB support:
 * Copyright (c) 2012 Aeroflex Gaisler AB.
 * Author: Andreas Larsson <andreas@gaisler.com>
 *
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 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/fsl_devices.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/types.h>
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#include "spi-fsl-lib.h"
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#include "spi-fsl-cpm.h"
#include "spi-fsl-spi.h"
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#define TYPE_FSL	0
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#define TYPE_GRLIB	1
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struct fsl_spi_match_data {
	int type;
};

static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
	.type = TYPE_FSL,
};

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static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
	.type = TYPE_GRLIB,
};

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static const struct of_device_id of_fsl_spi_match[] = {
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	{
		.compatible = "fsl,spi",
		.data = &of_fsl_spi_fsl_config,
	},
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	{
		.compatible = "aeroflexgaisler,spictrl",
		.data = &of_fsl_spi_grlib_config,
	},
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	{}
};
MODULE_DEVICE_TABLE(of, of_fsl_spi_match);

static int fsl_spi_get_type(struct device *dev)
{
	const struct of_device_id *match;

	if (dev->of_node) {
		match = of_match_node(of_fsl_spi_match, dev->of_node);
		if (match && match->data)
			return ((struct fsl_spi_match_data *)match->data)->type;
	}
	return TYPE_FSL;
}

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static void fsl_spi_change_mode(struct spi_device *spi)
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{
	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
	struct spi_mpc8xxx_cs *cs = spi->controller_state;
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	struct fsl_spi_reg *reg_base = mspi->reg_base;
	__be32 __iomem *mode = &reg_base->mode;
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	unsigned long flags;

	if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
		return;

	/* Turn off IRQs locally to minimize time that SPI is disabled. */
	local_irq_save(flags);

	/* Turn off SPI unit prior changing mode */
	mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);

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	/* When in CPM mode, we need to reinit tx and rx. */
	if (mspi->flags & SPI_CPM_MODE) {
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		fsl_spi_cpm_reinit_txrx(mspi);
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	}
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	mpc8xxx_spi_write_reg(mode, cs->hw_mode);
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	local_irq_restore(flags);
}

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static void fsl_spi_chipselect(struct spi_device *spi, int value)
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{
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	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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	struct fsl_spi_platform_data *pdata;
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	bool pol = spi->mode & SPI_CS_HIGH;
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	struct spi_mpc8xxx_cs	*cs = spi->controller_state;
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	pdata = spi->dev.parent->parent->platform_data;

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	if (value == BITBANG_CS_INACTIVE) {
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		if (pdata->cs_control)
			pdata->cs_control(spi, !pol);
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	}

	if (value == BITBANG_CS_ACTIVE) {
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		mpc8xxx_spi->rx_shift = cs->rx_shift;
		mpc8xxx_spi->tx_shift = cs->tx_shift;
		mpc8xxx_spi->get_rx = cs->get_rx;
		mpc8xxx_spi->get_tx = cs->get_tx;
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		fsl_spi_change_mode(spi);
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		if (pdata->cs_control)
			pdata->cs_control(spi, pol);
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	}
}

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static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
				      int bits_per_word, int msb_first)
{
	*rx_shift = 0;
	*tx_shift = 0;
	if (msb_first) {
		if (bits_per_word <= 8) {
			*rx_shift = 16;
			*tx_shift = 24;
		} else if (bits_per_word <= 16) {
			*rx_shift = 16;
			*tx_shift = 16;
		}
	} else {
		if (bits_per_word <= 8)
			*rx_shift = 8;
	}
}

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static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
				     int bits_per_word, int msb_first)
{
	*rx_shift = 0;
	*tx_shift = 0;
	if (bits_per_word <= 16) {
		if (msb_first) {
			*rx_shift = 16; /* LSB in bit 16 */
			*tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
		} else {
			*rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
		}
	}
}

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static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
				struct spi_device *spi,
				struct mpc8xxx_spi *mpc8xxx_spi,
				int bits_per_word)
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{
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	cs->rx_shift = 0;
	cs->tx_shift = 0;
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	if (bits_per_word <= 8) {
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		cs->get_rx = mpc8xxx_spi_rx_buf_u8;
		cs->get_tx = mpc8xxx_spi_tx_buf_u8;
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	} else if (bits_per_word <= 16) {
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		cs->get_rx = mpc8xxx_spi_rx_buf_u16;
		cs->get_tx = mpc8xxx_spi_tx_buf_u16;
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	} else if (bits_per_word <= 32) {
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		cs->get_rx = mpc8xxx_spi_rx_buf_u32;
		cs->get_tx = mpc8xxx_spi_tx_buf_u32;
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	} else
		return -EINVAL;

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	if (mpc8xxx_spi->set_shifts)
		mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
					bits_per_word,
					!(spi->mode & SPI_LSB_FIRST));

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	mpc8xxx_spi->rx_shift = cs->rx_shift;
	mpc8xxx_spi->tx_shift = cs->tx_shift;
	mpc8xxx_spi->get_rx = cs->get_rx;
	mpc8xxx_spi->get_tx = cs->get_tx;
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	return bits_per_word;
}

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static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
				struct spi_device *spi,
				int bits_per_word)
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{
	/* QE uses Little Endian for words > 8
	 * so transform all words > 8 into 8 bits
	 * Unfortnatly that doesn't work for LSB so
	 * reject these for now */
	/* Note: 32 bits word, LSB works iff
	 * tfcr/rfcr is set to CPMFCR_GBL */
	if (spi->mode & SPI_LSB_FIRST &&
	    bits_per_word > 8)
		return -EINVAL;
	if (bits_per_word > 8)
		return 8; /* pretend its 8 bits */
	return bits_per_word;
}

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static int fsl_spi_setup_transfer(struct spi_device *spi,
					struct spi_transfer *t)
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{
	struct mpc8xxx_spi *mpc8xxx_spi;
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	int bits_per_word = 0;
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	u8 pm;
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	u32 hz = 0;
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	struct spi_mpc8xxx_cs	*cs = spi->controller_state;

	mpc8xxx_spi = spi_master_get_devdata(spi->master);

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	if (!hz)
		hz = spi->max_speed_hz;

	if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
		bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
							   mpc8xxx_spi,
							   bits_per_word);
	else if (mpc8xxx_spi->flags & SPI_QE)
		bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
							  bits_per_word);

	if (bits_per_word < 0)
		return bits_per_word;

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	if (bits_per_word == 32)
		bits_per_word = 0;
	else
		bits_per_word = bits_per_word - 1;

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	/* mask out bits we are going to set */
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	cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
				  | SPMODE_PM(0xF));

	cs->hw_mode |= SPMODE_LEN(bits_per_word);

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	if ((mpc8xxx_spi->spibrg / hz) > 64) {
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		cs->hw_mode |= SPMODE_DIV16;
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		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
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		WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
			  "Will use %d Hz instead.\n", dev_name(&spi->dev),
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			  hz, mpc8xxx_spi->spibrg / 1024);
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		if (pm > 16)
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			pm = 16;
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	} else {
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		pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
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	}
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	if (pm)
		pm--;

	cs->hw_mode |= SPMODE_PM(pm);
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	fsl_spi_change_mode(spi);
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	return 0;
}
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static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
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				struct spi_transfer *t, unsigned int len)
{
	u32 word;
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	struct fsl_spi_reg *reg_base = mspi->reg_base;
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	mspi->count = len;

	/* enable rx ints */
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	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
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	/* transmit word */
	word = mspi->get_tx(mspi);
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	mpc8xxx_spi_write_reg(&reg_base->transmit, word);
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	return 0;
}

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static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
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			    bool is_dma_mapped)
{
	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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	struct fsl_spi_reg *reg_base;
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	unsigned int len = t->len;
	u8 bits_per_word;
	int ret;
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	reg_base = mpc8xxx_spi->reg_base;
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	bits_per_word = spi->bits_per_word;
	if (t->bits_per_word)
		bits_per_word = t->bits_per_word;
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	if (bits_per_word > 8) {
		/* invalid length? */
		if (len & 1)
			return -EINVAL;
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		len /= 2;
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	}
	if (bits_per_word > 16) {
		/* invalid length? */
		if (len & 1)
			return -EINVAL;
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		len /= 2;
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	}

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	mpc8xxx_spi->tx = t->tx_buf;
	mpc8xxx_spi->rx = t->rx_buf;
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	reinit_completion(&mpc8xxx_spi->done);
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	if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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		ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
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	else
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		ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
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	if (ret)
		return ret;
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	wait_for_completion(&mpc8xxx_spi->done);
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	/* disable rx ints */
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	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
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	if (mpc8xxx_spi->flags & SPI_CPM_MODE)
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		fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
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	return mpc8xxx_spi->count;
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}

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static int fsl_spi_do_one_msg(struct spi_master *master,
			      struct spi_message *m)
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{
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	struct spi_device *spi = m->spi;
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	struct spi_transfer *t, *first;
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	unsigned int cs_change;
	const int nsecs = 50;
	int status;

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	/* Don't allow changes if CS is active */
	first = list_first_entry(&m->transfers, struct spi_transfer,
			transfer_list);
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	list_for_each_entry(t, &m->transfers, transfer_list) {
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		if ((first->bits_per_word != t->bits_per_word) ||
			(first->speed_hz != t->speed_hz)) {
			dev_err(&spi->dev,
				"bits_per_word/speed_hz should be same for the same SPI transfer\n");
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			return -EINVAL;
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		}
	}
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	cs_change = 1;
	status = -EINVAL;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->bits_per_word || t->speed_hz) {
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			if (cs_change)
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				status = fsl_spi_setup_transfer(spi, t);
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			if (status < 0)
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				break;
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		}
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		if (cs_change) {
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			fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
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			ndelay(nsecs);
		}
		cs_change = t->cs_change;
		if (t->len)
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			status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
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		if (status) {
			status = -EMSGSIZE;
			break;
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		}
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		m->actual_length += t->len;
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		if (t->delay_usecs)
			udelay(t->delay_usecs);
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		if (cs_change) {
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			ndelay(nsecs);
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			fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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			ndelay(nsecs);
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		}
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	}

	m->status = status;
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	spi_finalize_current_message(master);
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	if (status || !cs_change) {
		ndelay(nsecs);
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		fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
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	}

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	fsl_spi_setup_transfer(spi, NULL);
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	return 0;
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}

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static int fsl_spi_setup(struct spi_device *spi)
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{
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	struct mpc8xxx_spi *mpc8xxx_spi;
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	struct fsl_spi_reg *reg_base;
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	int retval;
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	u32 hw_mode;
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	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
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	if (!spi->max_speed_hz)
		return -EINVAL;

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	if (!cs) {
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		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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		if (!cs)
			return -ENOMEM;
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		spi_set_ctldata(spi, cs);
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	}
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	mpc8xxx_spi = spi_master_get_devdata(spi->master);
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	reg_base = mpc8xxx_spi->reg_base;

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	hw_mode = cs->hw_mode; /* Save original settings */
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	cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
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	/* mask out bits we are going to set */
	cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
			 | SPMODE_REV | SPMODE_LOOP);

	if (spi->mode & SPI_CPHA)
		cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
	if (spi->mode & SPI_CPOL)
		cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
	if (!(spi->mode & SPI_LSB_FIRST))
		cs->hw_mode |= SPMODE_REV;
	if (spi->mode & SPI_LOOP)
		cs->hw_mode |= SPMODE_LOOP;

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	retval = fsl_spi_setup_transfer(spi, NULL);
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	if (retval < 0) {
		cs->hw_mode = hw_mode; /* Restore settings */
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		return retval;
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	}
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	if (mpc8xxx_spi->type == TYPE_GRLIB) {
		if (gpio_is_valid(spi->cs_gpio)) {
			int desel;

			retval = gpio_request(spi->cs_gpio,
					      dev_name(&spi->dev));
			if (retval)
				return retval;

			desel = !(spi->mode & SPI_CS_HIGH);
			retval = gpio_direction_output(spi->cs_gpio, desel);
			if (retval) {
				gpio_free(spi->cs_gpio);
				return retval;
			}
		} else if (spi->cs_gpio != -ENOENT) {
			if (spi->cs_gpio < 0)
				return spi->cs_gpio;
			return -EINVAL;
		}
		/* When spi->cs_gpio == -ENOENT, a hole in the phandle list
		 * indicates to use native chipselect if present, or allow for
		 * an always selected chip
		 */
	}

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	/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
	fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);

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	return 0;
}

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static void fsl_spi_cleanup(struct spi_device *spi)
{
	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
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	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
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	if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
		gpio_free(spi->cs_gpio);
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	kfree(cs);
	spi_set_ctldata(spi, NULL);
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}

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static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
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{
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	struct fsl_spi_reg *reg_base = mspi->reg_base;

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	/* We need handle RX first */
	if (events & SPIE_NE) {
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		u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
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		if (mspi->rx)
			mspi->get_rx(rx_data, mspi);
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	}

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	if ((events & SPIE_NF) == 0)
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		/* spin until TX is done */
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		while (((events =
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			mpc8xxx_spi_read_reg(&reg_base->event)) &
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						SPIE_NF) == 0)
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			cpu_relax();
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	/* Clear the events */
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	mpc8xxx_spi_write_reg(&reg_base->event, events);
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	mspi->count -= 1;
	if (mspi->count) {
		u32 word = mspi->get_tx(mspi);

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		mpc8xxx_spi_write_reg(&reg_base->transmit, word);
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	} else {
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		complete(&mspi->done);
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	}
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}
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static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
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{
	struct mpc8xxx_spi *mspi = context_data;
	irqreturn_t ret = IRQ_NONE;
	u32 events;
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	struct fsl_spi_reg *reg_base = mspi->reg_base;
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	/* Get interrupt events(tx/rx) */
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	events = mpc8xxx_spi_read_reg(&reg_base->event);
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	if (events)
		ret = IRQ_HANDLED;

	dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);

	if (mspi->flags & SPI_CPM_MODE)
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		fsl_spi_cpm_irq(mspi, events);
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	else
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		fsl_spi_cpu_irq(mspi, events);
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	return ret;
}
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static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
{
	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
	u32 slvsel;
	u16 cs = spi->chip_select;

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	if (gpio_is_valid(spi->cs_gpio)) {
		gpio_set_value(spi->cs_gpio, on);
	} else if (cs < mpc8xxx_spi->native_chipselects) {
		slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
		slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
		mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
	}
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}

static void fsl_spi_grlib_probe(struct device *dev)
{
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	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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	struct spi_master *master = dev_get_drvdata(dev);
	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
	int mbits;
	u32 capabilities;

	capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);

	mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
	mbits = SPCAP_MAXWLEN(capabilities);
	if (mbits)
		mpc8xxx_spi->max_bits_per_word = mbits + 1;

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	mpc8xxx_spi->native_chipselects = 0;
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	if (SPCAP_SSEN(capabilities)) {
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		mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
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		mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
	}
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	master->num_chipselect = mpc8xxx_spi->native_chipselects;
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	pdata->cs_control = fsl_spi_grlib_cs_control;
}

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static struct spi_master * fsl_spi_probe(struct device *dev,
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		struct resource *mem, unsigned int irq)
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{
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	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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	struct spi_master *master;
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	struct mpc8xxx_spi *mpc8xxx_spi;
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	struct fsl_spi_reg *reg_base;
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	u32 regval;
	int ret = 0;

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	master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
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	if (master == NULL) {
		ret = -ENOMEM;
		goto err;
	}

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	dev_set_drvdata(dev, master);
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	mpc8xxx_spi_probe(dev, mem, irq);
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	master->setup = fsl_spi_setup;
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	master->cleanup = fsl_spi_cleanup;
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	master->transfer_one_message = fsl_spi_do_one_msg;
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	mpc8xxx_spi = spi_master_get_devdata(master);
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	mpc8xxx_spi->max_bits_per_word = 32;
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	mpc8xxx_spi->type = fsl_spi_get_type(dev);
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	ret = fsl_spi_cpm_init(mpc8xxx_spi);
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	if (ret)
		goto err_cpm_init;

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	mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
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	if (IS_ERR(mpc8xxx_spi->reg_base)) {
		ret = PTR_ERR(mpc8xxx_spi->reg_base);
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		goto err_probe;
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	}

	if (mpc8xxx_spi->type == TYPE_GRLIB)
		fsl_spi_grlib_probe(dev);

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	master->bits_per_word_mask =
		(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
		SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);

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	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
		mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;

	if (mpc8xxx_spi->set_shifts)
		/* 8 bits per word and MSB first */
		mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
					&mpc8xxx_spi->tx_shift, 8, 1);
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	/* Register for SPI Interrupt */
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	ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
			       0, "fsl_spi", mpc8xxx_spi);
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	if (ret != 0)
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		goto err_probe;
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	reg_base = mpc8xxx_spi->reg_base;
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	/* SPI controller initializations */
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	mpc8xxx_spi_write_reg(&reg_base->mode, 0);
	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
	mpc8xxx_spi_write_reg(&reg_base->command, 0);
	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
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	/* Enable SPI interface */
	regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
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	if (mpc8xxx_spi->max_bits_per_word < 8) {
		regval &= ~SPMODE_LEN(0xF);
		regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
	}
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	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
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		regval |= SPMODE_OP;

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	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
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	ret = devm_spi_register_master(dev, master);
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	if (ret < 0)
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		goto err_probe;
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	dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
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		 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
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	return master;
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err_probe:
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	fsl_spi_cpm_free(mpc8xxx_spi);
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err_cpm_init:
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	spi_master_put(master);
err:
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	return ERR_PTR(ret);
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}

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static void fsl_spi_cs_control(struct spi_device *spi, bool on)
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{
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	struct device *dev = spi->dev.parent->parent;
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	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
	struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
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	u16 cs = spi->chip_select;
	int gpio = pinfo->gpios[cs];
	bool alow = pinfo->alow_flags[cs];

	gpio_set_value(gpio, on ^ alow);
}

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static int of_fsl_spi_get_chipselects(struct device *dev)
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{
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	struct device_node *np = dev->of_node;
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	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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	struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
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	int ngpios;
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	int i = 0;
	int ret;

	ngpios = of_gpio_count(np);
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	if (ngpios <= 0) {
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		/*
		 * SPI w/o chip-select line. One SPI device is still permitted
		 * though.
		 */
		pdata->max_chipselect = 1;
		return 0;
	}

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	pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
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	if (!pinfo->gpios)
		return -ENOMEM;
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	memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
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	pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
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				    GFP_KERNEL);
	if (!pinfo->alow_flags) {
		ret = -ENOMEM;
		goto err_alloc_flags;
	}

	for (; i < ngpios; i++) {
		int gpio;
		enum of_gpio_flags flags;

		gpio = of_get_gpio_flags(np, i, &flags);
		if (!gpio_is_valid(gpio)) {
			dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
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			ret = gpio;
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			goto err_loop;
		}

		ret = gpio_request(gpio, dev_name(dev));
		if (ret) {
			dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
			goto err_loop;
		}

		pinfo->gpios[i] = gpio;
		pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;

		ret = gpio_direction_output(pinfo->gpios[i],
					    pinfo->alow_flags[i]);
		if (ret) {
			dev_err(dev, "can't set output direction for gpio "
				"#%d: %d\n", i, ret);
			goto err_loop;
		}
	}

	pdata->max_chipselect = ngpios;
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	pdata->cs_control = fsl_spi_cs_control;
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	return 0;

err_loop:
	while (i >= 0) {
		if (gpio_is_valid(pinfo->gpios[i]))
			gpio_free(pinfo->gpios[i]);
		i--;
	}

	kfree(pinfo->alow_flags);
	pinfo->alow_flags = NULL;
err_alloc_flags:
	kfree(pinfo->gpios);
	pinfo->gpios = NULL;
	return ret;
}

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static int of_fsl_spi_free_chipselects(struct device *dev)
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{
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	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
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	struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
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	int i;

	if (!pinfo->gpios)
		return 0;

	for (i = 0; i < pdata->max_chipselect; i++) {
		if (gpio_is_valid(pinfo->gpios[i]))
			gpio_free(pinfo->gpios[i]);
	}

	kfree(pinfo->gpios);
	kfree(pinfo->alow_flags);
	return 0;
}

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static int of_fsl_spi_probe(struct platform_device *ofdev)
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{
	struct device *dev = &ofdev->dev;
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	struct device_node *np = ofdev->dev.of_node;
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	struct spi_master *master;
	struct resource mem;
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	int irq, type;
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	int ret = -ENOMEM;

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	ret = of_mpc8xxx_spi_probe(ofdev);
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	if (ret)
		return ret;
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	type = fsl_spi_get_type(&ofdev->dev);
	if (type == TYPE_FSL) {
		ret = of_fsl_spi_get_chipselects(dev);
		if (ret)
			goto err;
	}
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	ret = of_address_to_resource(np, 0, &mem);
	if (ret)
		goto err;

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	irq = irq_of_parse_and_map(np, 0);
	if (!irq) {
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		ret = -EINVAL;
		goto err;
	}

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	master = fsl_spi_probe(dev, &mem, irq);
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	if (IS_ERR(master)) {
		ret = PTR_ERR(master);
		goto err;
	}

	return 0;

err:
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	if (type == TYPE_FSL)
		of_fsl_spi_free_chipselects(dev);
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	return ret;
}

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static int of_fsl_spi_remove(struct platform_device *ofdev)
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{
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	struct spi_master *master = platform_get_drvdata(ofdev);
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	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
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	fsl_spi_cpm_free(mpc8xxx_spi);
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	if (mpc8xxx_spi->type == TYPE_FSL)
		of_fsl_spi_free_chipselects(&ofdev->dev);
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	return 0;
}

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static struct platform_driver of_fsl_spi_driver = {
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	.driver = {
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		.name = "fsl_spi",
		.of_match_table = of_fsl_spi_match,
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	},
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	.probe		= of_fsl_spi_probe,
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	.remove		= of_fsl_spi_remove,
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};

#ifdef CONFIG_MPC832x_RDB
/*
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 * XXX XXX XXX
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 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 * only. The driver should go away soon, since newer MPC8323E-RDB's device
 * tree can work with OpenFirmware driver. But for now we support old trees
 * as well.
 */
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static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
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{
	struct resource *mem;
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	int irq;
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	struct spi_master *master;

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	if (!dev_get_platdata(&pdev->dev))
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		return -EINVAL;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem)
		return -EINVAL;

	irq = platform_get_irq(pdev, 0);
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	if (irq <= 0)
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		return -EINVAL;

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	master = fsl_spi_probe(&pdev->dev, mem, irq);
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	return PTR_ERR_OR_ZERO(master);
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}

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static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
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{
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	struct spi_master *master = platform_get_drvdata(pdev);
	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);

	fsl_spi_cpm_free(mpc8xxx_spi);

	return 0;
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}

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MODULE_ALIAS("platform:mpc8xxx_spi");
static struct platform_driver mpc8xxx_spi_driver = {
	.probe = plat_mpc8xxx_spi_probe,
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	.remove = plat_mpc8xxx_spi_remove,
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	.driver = {
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		.name = "mpc8xxx_spi",
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	},
};

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static bool legacy_driver_failed;

static void __init legacy_driver_register(void)
{
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	legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
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}

static void __exit legacy_driver_unregister(void)
{
	if (legacy_driver_failed)
		return;
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	platform_driver_unregister(&mpc8xxx_spi_driver);
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}
#else
static void __init legacy_driver_register(void) {}
static void __exit legacy_driver_unregister(void) {}
#endif /* CONFIG_MPC832x_RDB */

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static int __init fsl_spi_init(void)
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{
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	legacy_driver_register();
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	return platform_driver_register(&of_fsl_spi_driver);
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}
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module_init(fsl_spi_init);
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static void __exit fsl_spi_exit(void)
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{
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	platform_driver_unregister(&of_fsl_spi_driver);
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	legacy_driver_unregister();
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}
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module_exit(fsl_spi_exit);
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MODULE_AUTHOR("Kumar Gala");
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MODULE_DESCRIPTION("Simple Freescale SPI Driver");
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MODULE_LICENSE("GPL");