amd64_edac.c 76.3 KB
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#include "amd64_edac.h"
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#include <asm/amd_nb.h>
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static struct edac_pci_ctl_info *pci_ctl;
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static int report_gart_errors;
module_param(report_gart_errors, int, 0644);

/*
 * Set by command line parameter. If BIOS has enabled the ECC, this override is
 * cleared to prevent re-enabling the hardware by this driver.
 */
static int ecc_enable_override;
module_param(ecc_enable_override, int, 0644);

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static struct msr __percpu *msrs;
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/* Per-node stuff */
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static struct ecc_settings **ecc_stngs;
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/*
 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
 * or higher value'.
 *
 *FIXME: Produce a better mapping/linearisation.
 */
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static const struct scrubrate {
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       u32 scrubval;           /* bit pattern for scrub rate */
       u32 bandwidth;          /* bandwidth consumed (bytes/sec) */
} scrubrates[] = {
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	{ 0x01, 1600000000UL},
	{ 0x02, 800000000UL},
	{ 0x03, 400000000UL},
	{ 0x04, 200000000UL},
	{ 0x05, 100000000UL},
	{ 0x06, 50000000UL},
	{ 0x07, 25000000UL},
	{ 0x08, 12284069UL},
	{ 0x09, 6274509UL},
	{ 0x0A, 3121951UL},
	{ 0x0B, 1560975UL},
	{ 0x0C, 781440UL},
	{ 0x0D, 390720UL},
	{ 0x0E, 195300UL},
	{ 0x0F, 97650UL},
	{ 0x10, 48854UL},
	{ 0x11, 24427UL},
	{ 0x12, 12213UL},
	{ 0x13, 6101UL},
	{ 0x14, 3051UL},
	{ 0x15, 1523UL},
	{ 0x16, 761UL},
	{ 0x00, 0UL},        /* scrubbing off */
};

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int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
			       u32 *val, const char *func)
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{
	int err = 0;

	err = pci_read_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error reading F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
				u32 val, const char *func)
{
	int err = 0;

	err = pci_write_config_dword(pdev, offset, val);
	if (err)
		amd64_warn("%s: error writing to F%dx%03x.\n",
			   func, PCI_FUNC(pdev->devfn), offset);

	return err;
}

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/*
 * Select DCT to which PCI cfg accesses are routed
 */
static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
{
	u32 reg = 0;

	amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
	reg &= (pvt->model == 0x30) ? ~3 : ~1;
	reg |= dct;
	amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
}

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/*
 *
 * Depending on the family, F2 DCT reads need special handling:
 *
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 * K8: has a single DCT only and no address offsets >= 0x100
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 *
 * F10h: each DCT has its own set of regs
 *	DCT0 -> F2x040..
 *	DCT1 -> F2x140..
 *
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 * F16h: has only 1 DCT
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 *
 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
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 */
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static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
					 int offset, u32 *val)
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{
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	switch (pvt->fam) {
	case 0xf:
		if (dct || offset >= 0x100)
			return -EINVAL;
		break;
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	case 0x10:
		if (dct) {
			/*
			 * Note: If ganging is enabled, barring the regs
			 * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
			 * return 0. (cf. Section 2.8.1 F10h BKDG)
			 */
			if (dct_ganging_enabled(pvt))
				return 0;
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			offset += 0x100;
		}
		break;
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	case 0x15:
		/*
		 * F15h: F2x1xx addresses do not map explicitly to DCT1.
		 * We should select which DCT we access using F1x10C[DctCfgSel]
		 */
		dct = (dct && pvt->model == 0x30) ? 3 : dct;
		f15h_select_dct(pvt, dct);
		break;
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	case 0x16:
		if (dct)
			return -EINVAL;
		break;
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	default:
		break;
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	}
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	return amd64_read_pci_cfg(pvt->F2, offset, val);
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}

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/*
 * Memory scrubber control interface. For K8, memory scrubbing is handled by
 * hardware and can involve L2 cache, dcache as well as the main memory. With
 * F10, this is extended to L3 cache scrubbing on CPU models sporting that
 * functionality.
 *
 * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
 * bytes/sec for the setting.
 *
 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
 * other archs, we might not have access to the caches directly.
 */

/*
 * scan the scrub rate mapping table for a close or matching bandwidth value to
 * issue. If requested is too big, then use last maximum value found.
 */
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static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
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{
	u32 scrubval;
	int i;

	/*
	 * map the configured rate (new_bw) to a value specific to the AMD64
	 * memory controller and apply to register. Search for the first
	 * bandwidth entry that is greater or equal than the setting requested
	 * and program that. If at last entry, turn off DRAM scrubbing.
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	 *
	 * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
	 * by falling back to the last element in scrubrates[].
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	 */
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	for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
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		/*
		 * skip scrub rates which aren't recommended
		 * (see F10 BKDG, F3x58)
		 */
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		if (scrubrates[i].scrubval < min_rate)
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			continue;

		if (scrubrates[i].bandwidth <= new_bw)
			break;
	}

	scrubval = scrubrates[i].scrubval;

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	if (pvt->fam == 0x15 && pvt->model == 0x60) {
		f15h_select_dct(pvt, 0);
		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
		f15h_select_dct(pvt, 1);
		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
	} else {
		pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
	}
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	if (scrubval)
		return scrubrates[i].bandwidth;

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	return 0;
}

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static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
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	u32 min_scrubrate = 0x5;
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	if (pvt->fam == 0xf)
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		min_scrubrate = 0x0;

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	if (pvt->fam == 0x15) {
		/* Erratum #505 */
		if (pvt->model < 0x10)
			f15h_select_dct(pvt, 0);
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		if (pvt->model == 0x60)
			min_scrubrate = 0x6;
	}
	return __set_scrub_rate(pvt, bw, min_scrubrate);
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}

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static int get_scrub_rate(struct mem_ctl_info *mci)
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{
	struct amd64_pvt *pvt = mci->pvt_info;
	u32 scrubval = 0;
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	int i, retval = -EINVAL;
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	if (pvt->fam == 0x15) {
		/* Erratum #505 */
		if (pvt->model < 0x10)
			f15h_select_dct(pvt, 0);
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		if (pvt->model == 0x60)
			amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
	} else
		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
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	scrubval = scrubval & 0x001F;

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	for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
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		if (scrubrates[i].scrubval == scrubval) {
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			retval = scrubrates[i].bandwidth;
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			break;
		}
	}
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	return retval;
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}

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/*
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 * returns true if the SysAddr given by sys_addr matches the
 * DRAM base/limit associated with node_id
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 */
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static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
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{
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	u64 addr;
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	/* The K8 treats this as a 40-bit value.  However, bits 63-40 will be
	 * all ones if the most significant implemented address bit is 1.
	 * Here we discard bits 63-40.  See section 3.4.2 of AMD publication
	 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
	 * Application Programming.
	 */
	addr = sys_addr & 0x000000ffffffffffull;

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	return ((addr >= get_dram_base(pvt, nid)) &&
		(addr <= get_dram_limit(pvt, nid)));
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}

/*
 * Attempt to map a SysAddr to a node. On success, return a pointer to the
 * mem_ctl_info structure for the node that the SysAddr maps to.
 *
 * On failure, return NULL.
 */
static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
						u64 sys_addr)
{
	struct amd64_pvt *pvt;
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	u8 node_id;
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	u32 intlv_en, bits;

	/*
	 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
	 * 3.4.4.2) registers to map the SysAddr to a node ID.
	 */
	pvt = mci->pvt_info;

	/*
	 * The value of this field should be the same for all DRAM Base
	 * registers.  Therefore we arbitrarily choose to read it from the
	 * register for node 0.
	 */
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	intlv_en = dram_intlv_en(pvt, 0);
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	if (intlv_en == 0) {
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		for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
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			if (base_limit_match(pvt, sys_addr, node_id))
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				goto found;
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		}
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		goto err_no_match;
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	}

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	if (unlikely((intlv_en != 0x01) &&
		     (intlv_en != 0x03) &&
		     (intlv_en != 0x07))) {
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		amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
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		return NULL;
	}

	bits = (((u32) sys_addr) >> 12) & intlv_en;

	for (node_id = 0; ; ) {
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		if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
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			break;	/* intlv_sel field matches */

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		if (++node_id >= DRAM_RANGES)
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			goto err_no_match;
	}

	/* sanity test for sys_addr */
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	if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
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		amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
			   "range for node %d with node interleaving enabled.\n",
			   __func__, sys_addr, node_id);
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		return NULL;
	}

found:
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	return edac_mc_find((int)node_id);
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err_no_match:
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	edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
		 (unsigned long)sys_addr);
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	return NULL;
}
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/*
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 * compute the CS base address of the @csrow on the DRAM controller @dct.
 * For details see F2x[5C:40] in the processor's BKDG
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 */
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static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
				 u64 *base, u64 *mask)
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{
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	u64 csbase, csmask, base_bits, mask_bits;
	u8 addr_shift;
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
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		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow];
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		base_bits	= GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
		mask_bits	= GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
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		addr_shift	= 4;
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	/*
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	 * F16h and F15h, models 30h and later need two addr_shift values:
	 * 8 for high and 6 for low (cf. F16h BKDG).
	 */
	} else if (pvt->fam == 0x16 ||
		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {
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		csbase          = pvt->csels[dct].csbases[csrow];
		csmask          = pvt->csels[dct].csmasks[csrow >> 1];

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		*base  = (csbase & GENMASK_ULL(15,  5)) << 6;
		*base |= (csbase & GENMASK_ULL(30, 19)) << 8;
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		*mask = ~0ULL;
		/* poke holes for the csmask */
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		*mask &= ~((GENMASK_ULL(15, 5)  << 6) |
			   (GENMASK_ULL(30, 19) << 8));
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		*mask |= (csmask & GENMASK_ULL(15, 5))  << 6;
		*mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
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		return;
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	} else {
		csbase		= pvt->csels[dct].csbases[csrow];
		csmask		= pvt->csels[dct].csmasks[csrow >> 1];
		addr_shift	= 8;
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		if (pvt->fam == 0x15)
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			base_bits = mask_bits =
				GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
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		else
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			base_bits = mask_bits =
				GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
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	}
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	*base  = (csbase & base_bits) << addr_shift;
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	*mask  = ~0ULL;
	/* poke holes for the csmask */
	*mask &= ~(mask_bits << addr_shift);
	/* OR them in */
	*mask |= (csmask & mask_bits) << addr_shift;
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}

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#define for_each_chip_select(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].b_cnt; i++)

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#define chip_select_base(i, dct, pvt) \
	pvt->csels[dct].csbases[i]

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#define for_each_chip_select_mask(i, dct, pvt) \
	for (i = 0; i < pvt->csels[dct].m_cnt; i++)

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/*
 * @input_addr is an InputAddr associated with the node given by mci. Return the
 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
 */
static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
{
	struct amd64_pvt *pvt;
	int csrow;
	u64 base, mask;

	pvt = mci->pvt_info;

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	for_each_chip_select(csrow, 0, pvt) {
		if (!csrow_enabled(csrow, 0, pvt))
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			continue;

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		get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);

		mask = ~mask;
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		if ((input_addr & mask) == (base & mask)) {
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			edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
				 (unsigned long)input_addr, csrow,
				 pvt->mc_node_id);
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			return csrow;
		}
	}
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	edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
		 (unsigned long)input_addr, pvt->mc_node_id);
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	return -1;
}

/*
 * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
 * for the node represented by mci. Info is passed back in *hole_base,
 * *hole_offset, and *hole_size.  Function returns 0 if info is valid or 1 if
 * info is invalid. Info may be invalid for either of the following reasons:
 *
 * - The revision of the node is not E or greater.  In this case, the DRAM Hole
 *   Address Register does not exist.
 *
 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
 *   indicating that its contents are not valid.
 *
 * The values passed back in *hole_base, *hole_offset, and *hole_size are
 * complete 32-bit values despite the fact that the bitfields in the DHAR
 * only represent bits 31-24 of the base and offset values.
 */
int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
			     u64 *hole_offset, u64 *hole_size)
{
	struct amd64_pvt *pvt = mci->pvt_info;

	/* only revE and later have the DRAM Hole Address Register */
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	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
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		edac_dbg(1, "  revision %d for node %d does not support DHAR\n",
			 pvt->ext_model, pvt->mc_node_id);
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		return 1;
	}

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	/* valid for Fam10h and above */
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	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this system\n");
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		return 1;
	}

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	if (!dhar_valid(pvt)) {
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		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this node %d\n",
			 pvt->mc_node_id);
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		return 1;
	}

	/* This node has Memory Hoisting */

	/* +------------------+--------------------+--------------------+-----
	 * | memory           | DRAM hole          | relocated          |
	 * | [0, (x - 1)]     | [x, 0xffffffff]    | addresses from     |
	 * |                  |                    | DRAM hole          |
	 * |                  |                    | [0x100000000,      |
	 * |                  |                    |  (0x100000000+     |
	 * |                  |                    |   (0xffffffff-x))] |
	 * +------------------+--------------------+--------------------+-----
	 *
	 * Above is a diagram of physical memory showing the DRAM hole and the
	 * relocated addresses from the DRAM hole.  As shown, the DRAM hole
	 * starts at address x (the base address) and extends through address
	 * 0xffffffff.  The DRAM Hole Address Register (DHAR) relocates the
	 * addresses in the hole so that they start at 0x100000000.
	 */

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	*hole_base = dhar_base(pvt);
	*hole_size = (1ULL << 32) - *hole_base;
512

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	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
					: k8_dhar_offset(pvt);
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	edac_dbg(1, "  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
		 pvt->mc_node_id, (unsigned long)*hole_base,
		 (unsigned long)*hole_offset, (unsigned long)*hole_size);
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	return 0;
}
EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info);

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/*
 * Return the DramAddr that the SysAddr given by @sys_addr maps to.  It is
 * assumed that sys_addr maps to the node given by mci.
 *
 * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
 * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
 * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
 * then it is also involved in translating a SysAddr to a DramAddr. Sections
 * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
 * These parts of the documentation are unclear. I interpret them as follows:
 *
 * When node n receives a SysAddr, it processes the SysAddr as follows:
 *
 * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
 *    Limit registers for node n. If the SysAddr is not within the range
 *    specified by the base and limit values, then node n ignores the Sysaddr
 *    (since it does not map to node n). Otherwise continue to step 2 below.
 *
 * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
 *    disabled so skip to step 3 below. Otherwise see if the SysAddr is within
 *    the range of relocated addresses (starting at 0x100000000) from the DRAM
 *    hole. If not, skip to step 3 below. Else get the value of the
 *    DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
 *    offset defined by this value from the SysAddr.
 *
 * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
 *    Base register for node n. To obtain the DramAddr, subtract the base
 *    address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
 */
static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
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	struct amd64_pvt *pvt = mci->pvt_info;
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	u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
557
	int ret;
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	dram_base = get_dram_base(pvt, pvt->mc_node_id);
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	ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset,
				      &hole_size);
	if (!ret) {
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		if ((sys_addr >= (1ULL << 32)) &&
		    (sys_addr < ((1ULL << 32) + hole_size))) {
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			/* use DHAR to translate SysAddr to DramAddr */
			dram_addr = sys_addr - hole_offset;

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			edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
				 (unsigned long)sys_addr,
				 (unsigned long)dram_addr);
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			return dram_addr;
		}
	}

	/*
	 * Translate the SysAddr to a DramAddr as shown near the start of
	 * section 3.4.4 (p. 70).  Although sys_addr is a 64-bit value, the k8
	 * only deals with 40-bit values.  Therefore we discard bits 63-40 of
	 * sys_addr below.  If bit 39 of sys_addr is 1 then the bits we
	 * discard are all 1s.  Otherwise the bits we discard are all 0s.  See
	 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
	 * Programmer's Manual Volume 1 Application Programming.
	 */
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	dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
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	edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
		 (unsigned long)sys_addr, (unsigned long)dram_addr);
590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620
	return dram_addr;
}

/*
 * @intlv_en is the value of the IntlvEn field from a DRAM Base register
 * (section 3.4.4.1).  Return the number of bits from a SysAddr that are used
 * for node interleaving.
 */
static int num_node_interleave_bits(unsigned intlv_en)
{
	static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
	int n;

	BUG_ON(intlv_en > 7);
	n = intlv_shift_table[intlv_en];
	return n;
}

/* Translate the DramAddr given by @dram_addr to an InputAddr. */
static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
{
	struct amd64_pvt *pvt;
	int intlv_shift;
	u64 input_addr;

	pvt = mci->pvt_info;

	/*
	 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
	 * concerning translating a DramAddr to an InputAddr.
	 */
621
	intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
622
	input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
623
		      (dram_addr & 0xfff);
624

625 626 627
	edac_dbg(2, "  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
		 intlv_shift, (unsigned long)dram_addr,
		 (unsigned long)input_addr);
628 629 630 631 632 633 634 635 636 637 638 639 640 641 642

	return input_addr;
}

/*
 * Translate the SysAddr represented by @sys_addr to an InputAddr.  It is
 * assumed that @sys_addr maps to the node given by mci.
 */
static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
{
	u64 input_addr;

	input_addr =
	    dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));

643
	edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",
644
		 (unsigned long)sys_addr, (unsigned long)input_addr);
645 646 647 648 649 650

	return input_addr;
}

/* Map the Error address to a PAGE and PAGE OFFSET. */
static inline void error_address_to_page_and_offset(u64 error_address,
651
						    struct err_info *err)
652
{
653 654
	err->page = (u32) (error_address >> PAGE_SHIFT);
	err->offset = ((u32) error_address) & ~PAGE_MASK;
655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671
}

/*
 * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
 * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
 * of a node that detected an ECC memory error.  mci represents the node that
 * the error address maps to (possibly different from the node that detected
 * the error).  Return the number of the csrow that sys_addr maps to, or -1 on
 * error.
 */
static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
{
	int csrow;

	csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));

	if (csrow == -1)
672 673
		amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
				  "address 0x%lx\n", (unsigned long)sys_addr);
674 675
	return csrow;
}
676

677
static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
678 679 680 681 682

/*
 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
 * are ECC capable.
 */
683
static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
684
{
685
	u8 bit;
686
	unsigned long edac_cap = EDAC_FLAG_NONE;
687

688
	bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
689 690 691
		? 19
		: 17;

692
	if (pvt->dclr0 & BIT(bit))
693 694 695 696 697
		edac_cap = EDAC_FLAG_SECDED;

	return edac_cap;
}

698
static void debug_display_dimm_sizes(struct amd64_pvt *, u8);
699

700
static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
701
{
702
	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
703

704 705 706 707 708 709 710 711 712 713 714 715 716
	if (pvt->dram_type == MEM_LRDDR3) {
		u32 dcsm = pvt->csels[chan].csmasks[0];
		/*
		 * It's assumed all LRDIMMs in a DCT are going to be of
		 * same 'type' until proven otherwise. So, use a cs
		 * value of '0' here to get dcsm value.
		 */
		edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
	}

	edac_dbg(1, "All DIMMs support ECC:%s\n",
		    (dclr & BIT(19)) ? "yes" : "no");

717

718 719
	edac_dbg(1, "  PAR/ERR parity: %s\n",
		 (dclr & BIT(8)) ?  "enabled" : "disabled");
720

721
	if (pvt->fam == 0x10)
722 723
		edac_dbg(1, "  DCT 128bit mode width: %s\n",
			 (dclr & BIT(11)) ?  "128b" : "64b");
724

725 726 727 728 729
	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
		 (dclr & BIT(12)) ?  "yes" : "no",
		 (dclr & BIT(13)) ?  "yes" : "no",
		 (dclr & BIT(14)) ?  "yes" : "no",
		 (dclr & BIT(15)) ?  "yes" : "no");
730 731
}

732
/* Display and decode various NB registers for debug purposes. */
733
static void dump_misc_regs(struct amd64_pvt *pvt)
734
{
735
	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
736

737 738
	edac_dbg(1, "  NB two channel DRAM capable: %s\n",
		 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
739

740 741 742
	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",
		 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
		 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
743

744
	debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
745

746
	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
747

748 749
	edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
		 pvt->dhar, dhar_base(pvt),
750 751
		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
				   : f10_dhar_offset(pvt));
752

753
	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
754

755
	debug_display_dimm_sizes(pvt, 0);
756

757
	/* everything below this point is Fam10h and above */
758
	if (pvt->fam == 0xf)
759
		return;
760

761
	debug_display_dimm_sizes(pvt, 1);
762

763
	amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
764

765
	/* Only if NOT ganged does dclr1 have valid info */
766
	if (!dct_ganging_enabled(pvt))
767
		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
768 769
}

770
/*
771
 * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
772
 */
773
static void prep_chip_selects(struct amd64_pvt *pvt)
774
{
775
	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
776 777
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
778
	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {
779 780
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
781
	} else {
782 783
		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
784 785 786 787
	}
}

/*
788
 * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
789
 */
790
static void read_dct_base_mask(struct amd64_pvt *pvt)
791
{
792
	int cs;
793

794
	prep_chip_selects(pvt);
795

796
	for_each_chip_select(cs, 0, pvt) {
797 798
		int reg0   = DCSB0 + (cs * 4);
		int reg1   = DCSB1 + (cs * 4);
799 800
		u32 *base0 = &pvt->csels[0].csbases[cs];
		u32 *base1 = &pvt->csels[1].csbases[cs];
801

802
		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
803 804
			edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",
				 cs, *base0, reg0);
805

806
		if (pvt->fam == 0xf)
807
			continue;
808

809
		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
810
			edac_dbg(0, "  DCSB1[%d]=0x%08x reg: F2x%x\n",
811 812
				 cs, *base1, (pvt->fam == 0x10) ? reg1
								: reg0);
813 814
	}

815
	for_each_chip_select_mask(cs, 0, pvt) {
816 817
		int reg0   = DCSM0 + (cs * 4);
		int reg1   = DCSM1 + (cs * 4);
818 819
		u32 *mask0 = &pvt->csels[0].csmasks[cs];
		u32 *mask1 = &pvt->csels[1].csmasks[cs];
820

821
		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
822 823
			edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",
				 cs, *mask0, reg0);
824

825
		if (pvt->fam == 0xf)
826
			continue;
827

828
		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
829
			edac_dbg(0, "    DCSM1[%d]=0x%08x reg: F2x%x\n",
830 831
				 cs, *mask1, (pvt->fam == 0x10) ? reg1
								: reg0);
832 833 834
	}
}

835
static void determine_memory_type(struct amd64_pvt *pvt)
836
{
837
	u32 dram_ctrl, dcsm;
838

839 840 841 842 843 844 845 846 847
	switch (pvt->fam) {
	case 0xf:
		if (pvt->ext_model >= K8_REV_F)
			goto ddr3;

		pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
		return;

	case 0x10:
848
		if (pvt->dchr0 & DDR3_MODE)
849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875
			goto ddr3;

		pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
		return;

	case 0x15:
		if (pvt->model < 0x60)
			goto ddr3;

		/*
		 * Model 0x60h needs special handling:
		 *
		 * We use a Chip Select value of '0' to obtain dcsm.
		 * Theoretically, it is possible to populate LRDIMMs of different
		 * 'Rank' value on a DCT. But this is not the common case. So,
		 * it's reasonable to assume all DIMMs are going to be of same
		 * 'type' until proven otherwise.
		 */
		amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl);
		dcsm = pvt->csels[0].csmasks[0];

		if (((dram_ctrl >> 8) & 0x7) == 0x2)
			pvt->dram_type = MEM_DDR4;
		else if (pvt->dclr0 & BIT(16))
			pvt->dram_type = MEM_DDR3;
		else if (dcsm & 0x3)
			pvt->dram_type = MEM_LRDDR3;
876
		else
877
			pvt->dram_type = MEM_RDDR3;
878

879 880 881 882 883 884 885 886 887 888
		return;

	case 0x16:
		goto ddr3;

	default:
		WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);
		pvt->dram_type = MEM_EMPTY;
	}
	return;
889

890 891
ddr3:
	pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
892 893
}

894
/* Get the number of DCT channels the memory controller is using. */
895 896
static int k8_early_channel_count(struct amd64_pvt *pvt)
{
897
	int flag;
898

899
	if (pvt->ext_model >= K8_REV_F)
900
		/* RevF (NPT) and later */
901
		flag = pvt->dclr0 & WIDTH_128;
902
	else
903 904 905 906 907 908 909 910 911
		/* RevE and earlier */
		flag = pvt->dclr0 & REVE_WIDTH_128;

	/* not used */
	pvt->dclr1 = 0;

	return (flag) ? 2 : 1;
}

912
/* On F10h and later ErrAddr is MC4_ADDR[47:1] */
913
static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
914
{
915 916
	u16 mce_nid = amd_get_nb_id(m->extcpu);
	struct mem_ctl_info *mci;
917 918
	u8 start_bit = 1;
	u8 end_bit   = 47;
919 920 921 922 923 924 925
	u64 addr;

	mci = edac_mc_find(mce_nid);
	if (!mci)
		return 0;

	pvt = mci->pvt_info;
926

927
	if (pvt->fam == 0xf) {
928 929 930 931
		start_bit = 3;
		end_bit   = 39;
	}

932
	addr = m->addr & GENMASK_ULL(end_bit, start_bit);
933 934 935 936

	/*
	 * Erratum 637 workaround
	 */
937
	if (pvt->fam == 0x15) {
938 939
		u64 cc6_base, tmp_addr;
		u32 tmp;
940
		u8 intlv_en;
941

942
		if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
943 944 945 946 947 948 949
			return addr;


		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
		intlv_en = tmp >> 21 & 0x7;

		/* add [47:27] + 3 trailing bits */
950
		cc6_base  = (tmp & GENMASK_ULL(20, 0)) << 3;
951 952 953 954 955 956 957 958

		/* reverse and add DramIntlvEn */
		cc6_base |= intlv_en ^ 0x7;

		/* pin at [47:24] */
		cc6_base <<= 24;

		if (!intlv_en)
959
			return cc6_base | (addr & GENMASK_ULL(23, 0));
960 961 962 963

		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);

							/* faster log2 */
964
		tmp_addr  = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
965 966

		/* OR DramIntlvSel into bits [14:12] */
967
		tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
968 969

		/* add remaining [11:0] bits from original MC4_ADDR */
970
		tmp_addr |= addr & GENMASK_ULL(11, 0);
971 972 973 974 975

		return cc6_base | tmp_addr;
	}

	return addr;
976 977
}

978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993
static struct pci_dev *pci_get_related_function(unsigned int vendor,
						unsigned int device,
						struct pci_dev *related)
{
	struct pci_dev *dev = NULL;

	while ((dev = pci_get_device(vendor, device, dev))) {
		if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
		    (dev->bus->number == related->bus->number) &&
		    (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
			break;
	}

	return dev;
}

994
static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
995
{
996
	struct amd_northbridge *nb;
997 998
	struct pci_dev *f1 = NULL;
	unsigned int pci_func;
999
	int off = range << 3;
1000
	u32 llim;
1001

1002 1003
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
1004

1005
	if (pvt->fam == 0xf)
1006
		return;
1007

1008 1009
	if (!dram_rw(pvt, range))
		return;
1010

1011 1012
	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);
	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
1013

1014
	/* F15h: factor in CC6 save area by reading dst node's limit reg */
1015
	if (pvt->fam != 0x15)
1016
		return;
1017

1018 1019 1020
	nb = node_to_amd_nb(dram_dst_node(pvt, range));
	if (WARN_ON(!nb))
		return;
1021

1022 1023 1024 1025 1026 1027
	if (pvt->model == 0x60)
		pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
	else if (pvt->model == 0x30)
		pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
	else
		pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1;
1028 1029

	f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc);
1030 1031
	if (WARN_ON(!f1))
		return;
1032

1033
	amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
1034

1035
	pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
1036

1037 1038
				    /* {[39:27],111b} */
	pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
1039

1040
	pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
1041

1042 1043 1044 1045
				    /* [47:40] */
	pvt->ranges[range].lim.hi |= llim >> 13;

	pci_dev_put(f1);
1046 1047
}

1048
static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
1049
				    struct err_info *err)
1050
{
1051
	struct amd64_pvt *pvt = mci->pvt_info;
1052

1053
	error_address_to_page_and_offset(sys_addr, err);
1054 1055 1056 1057 1058

	/*
	 * Find out which node the error address belongs to. This may be
	 * different from the node that detected the error.
	 */
1059 1060
	err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
	if (!err->src_mci) {
1061 1062
		amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
			     (unsigned long)sys_addr);
1063
		err->err_code = ERR_NODE;
1064 1065 1066 1067
		return;
	}

	/* Now map the sys_addr to a CSROW */
1068 1069 1070
	err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
	if (err->csrow < 0) {
		err->err_code = ERR_CSROW;
1071 1072 1073
		return;
	}

1074
	/* CHIPKILL enabled */
1075
	if (pvt->nbcfg & NBCFG_CHIPKILL) {
1076 1077
		err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
		if (err->channel < 0) {
1078 1079 1080 1081 1082
			/*
			 * Syndrome didn't map, so we don't know which of the
			 * 2 DIMMs is in error. So we need to ID 'both' of them
			 * as suspect.
			 */
1083
			amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
1084
				      "possible error reporting race\n",
1085 1086
				      err->syndrome);
			err->err_code = ERR_CHANNEL;
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097
			return;
		}
	} else {
		/*
		 * non-chipkill ecc mode
		 *
		 * The k8 documentation is unclear about how to determine the
		 * channel number when using non-chipkill memory.  This method
		 * was obtained from email communication with someone at AMD.
		 * (Wish the email was placed in this comment - norsk)
		 */
1098
		err->channel = ((sys_addr & BIT(3)) != 0);
1099 1100 1101
	}
}

1102
static int ddr2_cs_size(unsigned i, bool dct_width)
1103
{
1104
	unsigned shift = 0;
1105

1106 1107 1108 1109
	if (i <= 2)
		shift = i;
	else if (!(i & 0x1))
		shift = i >> 1;
1110
	else
1111
		shift = (i + 1) >> 1;
1112

1113 1114 1115 1116
	return 128 << (shift + !!dct_width);
}

static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
1117
				  unsigned cs_mode, int cs_mask_nr)
1118 1119 1120 1121 1122 1123 1124 1125
{
	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;

	if (pvt->ext_model >= K8_REV_F) {
		WARN_ON(cs_mode > 11);
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
	}
	else if (pvt->ext_model >= K8_REV_D) {
1126
		unsigned diff;
1127 1128
		WARN_ON(cs_mode > 10);

1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
		/*
		 * the below calculation, besides trying to win an obfuscated C
		 * contest, maps cs_mode values to DIMM chip select sizes. The
		 * mappings are:
		 *
		 * cs_mode	CS size (mb)
		 * =======	============
		 * 0		32
		 * 1		64
		 * 2		128
		 * 3		128
		 * 4		256
		 * 5		512
		 * 6		256
		 * 7		512
		 * 8		1024
		 * 9		1024
		 * 10		2048
		 *
		 * Basically, it calculates a value with which to shift the
		 * smallest CS size of 32MB.
		 *
		 * ddr[23]_cs_size have a similar purpose.
		 */
		diff = cs_mode/3 + (unsigned)(cs_mode > 5);

		return 32 << (cs_mode - diff);
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	}
	else {
		WARN_ON(cs_mode > 6);
		return 32 << cs_mode;
	}