1. 30 Mar, 2015 2 commits
  2. 27 Mar, 2015 2 commits
  3. 25 Mar, 2015 2 commits
  4. 24 Mar, 2015 4 commits
    • Mark Rutland's avatar
      arm64: head.S: ensure idmap_t0sz is visible · 0c20856c
      Mark Rutland authored
      We write idmap_t0sz with SCTLR_EL1.{C,M} clear, but we only have the
      guarnatee that the kernel Image is clean, not invalid in the caches, and
      therefore we might read a stale value once the MMU is enabled.
      This patch ensures we invalidate the corresponding cacheline after the
      write as we do for all other data written before we set SCTLR_EL1.{C.M},
      guaranteeing that the value will be visible later. We rely on the DSBs
      in __create_page_tables to complete the maintenance.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      CC: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Will Deacon's avatar
      arm64: pmu: add support for interrupt-affinity property · d5efd9cc
      Will Deacon authored
      Historically, the PMU devicetree bindings have expected SPIs to be
      listed in order of *logical* CPU number. This is problematic for
      bootloaders, especially when the boot CPU (logical ID 0) isn't listed
      first in the devicetree.
      This patch adds a new optional property, interrupt-affinity, to the
      PMU node which allows the interrupt affinity to be described using
      a list of phandled to CPU nodes, with each entry in the list
      corresponding to the SPI at the same index in the interrupts property.
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Will Deacon's avatar
      dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity · 71bbf038
      Will Deacon authored
      The current ARM PMU binding relies on the PMU interrupts being listed in
      CPU logical order, which the device-tree author simply cannot know
      anything about.
      This patch introduces a new "interrupt-affinity" property, which makes
      the relationship between the PMU interrupts and their corresponding
      CPU explicit.
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Mark Rutland's avatar
      arm64: head.S: ensure visibility of page tables · 91d57155
      Mark Rutland authored
      After writing the page tables, we use __inval_cache_range to invalidate
      any stale cache entries. Strongly Ordered memory accesses are not
      ordered w.r.t. cache maintenance instructions, and hence explicit memory
      barriers are required to provide this ordering. However,
      __inval_cache_range was written to be used on Normal Cacheable memory
      once the MMU and caches are on, and does not have any barriers prior to
      the DC instructions.
      This patch adds a DMB between the page tables being written and the
      corresponding cachelines being invalidated, ensuring that the
      invalidation makes the new data visible to subsequent cacheable
      accesses. A barrier is not required before the prior invalidate as we do
      not access the page table memory area prior to this, and earlier
      barriers in preserve_boot_args and set_cpu_boot_mode_flag ensures
      ordering w.r.t. any stores performed prior to entering Linux.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Fixes: c218bca7
       ("arm64: Relax the kernel cache requirements for boot")
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  5. 23 Mar, 2015 4 commits
  6. 19 Mar, 2015 18 commits
  7. 17 Mar, 2015 5 commits
    • Steve Capper's avatar
      arm64: Adjust EFI libstub object include logic · ad08fd49
      Steve Capper authored
      Commit f4f75ad5 ("efi: efistub: Convert into static library")
      introduced a static library for EFI stub, libstub.
      The EFI libstub directory is referenced by the kernel build system via
      a obj subdirectory rule in:
      Unfortunately, arm64 also references the EFI libstub via:
      libs-$(CONFIG_EFI_STUB) += drivers/firmware/efi/libstub/
      If we're unlucky, the kernel build system can enter libstub via two
      simultaneous threads resulting in build failures such as:
      fixdep: error opening depfile: drivers/firmware/efi/libstub/.efi-stub-helper.o.d: No such file or directory
      scripts/Makefile.build:257: recipe for target 'drivers/firmware/efi/libstub/efi-stub-helper.o' failed
      make[1]: *** [drivers/firmware/efi/libstub/efi-stub-helper.o] Error 2
      Makefile:939: recipe for target 'drivers/firmware/efi/libstub' failed
      make: *** [drivers/firmware/efi/libstub] Error 2
      make: *** Waiting for unfinished jobs....
      This patch adjusts the arm64 Makefile to reference the compiled library
      explicitly (as is currently done in x86), rather than the directory.
      Fixes: f4f75ad5
       efi: efistub: Convert into static library
      Signed-off-by: default avatarSteve Capper <steve.capper@linaro.org>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Mark Rutland's avatar
      arm64: log CPU boot modes · 667f3fd3
      Mark Rutland authored
      We currently don't log the boot mode for arm64 as we do for arm, and
      without KVM the user is provided with no indication as to which mode(s)
      CPUs were booted in, which can seriously hinder debugging in some cases.
      Add logging to the boot path once all CPUs are up. Where CPUs are
      mismatched in violation of the boot protocol, WARN and set a taint (as
      we do for CPU other CPU feature mismatches) given that the
      firmware/bootloader is buggy and should be fixed.
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Tested-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Mark Rutland's avatar
      arm64: fix hyp mode mismatch detection · 424a3838
      Mark Rutland authored
      Commit 828e9834
       ("arm64: head: create a new function for setting
      the boot_cpu_mode flag") added BOOT_CPU_MODE_EL1, a nonzero value
      replacing uses of zero. However it failed to update __boot_cpu_mode
      A CPU booted at EL2 writes BOOT_CPU_MODE_EL2 to __boot_cpu_mode[0], and
      a CPU booted at EL1 writes BOOT_CPU_MODE_EL1 to __boot_cpu_mode[1].
      Later is_hyp_mode_mismatched() determines there to be a mismatch if
      __boot_cpu_mode[0] != __boot_cpu_mode[1].
      If all CPUs are booted at EL1, __boot_cpu_mode[0] will be set to
      BOOT_CPU_MODE_EL1, but __boot_cpu_mode[1] will retain its initial value
      of zero, and is_hyp_mode_mismatched will erroneously determine that the
      boot modes are mismatched. This hasn't been a problem so far, but later
      patches which will make use of is_hyp_mode_mismatched() expect it to
      work correctly.
      This patch initialises __boot_cpu_mode[1] to BOOT_CPU_MODE_EL1, fixing
      the erroneous mismatch detection when all CPUs are booted at EL1.
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Tested-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Mark Rutland's avatar
      arm64: apply alternatives for !SMP kernels · 137650aa
      Mark Rutland authored
      Currently we only perform alternative patching for kernels built with
      CONFIG_SMP, as we call apply_alternatives_all() in smp.c, which is only
      built for CONFIG_SMP. Thus !SMP kernels may not have necessary
      alternatives patched in.
      This patch ensures that we call apply_alternatives_all() once all CPUs
      are booted, even for !SMP kernels, by having the smp_init_cpus() stub
      call this for !SMP kernels via up_late_init. A new wrapper,
      do_post_cpus_up_work, is added so we can hook other calls here later
      (e.g. boot mode logging).
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Fixes: e039ee4e
       ("arm64: add alternative runtime patching")
      Tested-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Reviewed-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Peter Crosthwaite's avatar
      arm64: Implement cpu_relax as yield · 1baa82f4
      Peter Crosthwaite authored
      ARM64 has the yield nop hint which has the intended semantics of
      cpu_relax. Implement.
      The immediate application is ARM CPU emulators. An emulator can take
      advantage of the yield hint to de-prioritise an emulated CPU in favor
      of other emulation tasks. QEMU A64 SMP emulation has yield awareness,
      and sees a significant boot time performance increase with this change.
      Signed-off-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  8. 15 Mar, 2015 3 commits
    • Linus Torvalds's avatar
      Linux 4.0-rc4 · 06e5801b
      Linus Torvalds authored
    • Linus Torvalds's avatar
      Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux · 08352086
      Linus Torvalds authored
      Pull drm fix from Dave Airlie:
       "An oops snuck in in an -rc3 patch, this fixes it"
      * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
        [PATCH] drm/mm: Fix support 4 GiB and larger ranges
    • Linus Torvalds's avatar
      Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux · 1ee89c51
      Linus Torvalds authored
      Pull clock framework fixes from Michael Turquette:
       "The clk fixes for 4.0-rc4 comprise three themes.
        First are the usual driver fixes for new regressions since v3.19.
        Second are fixes to the common clock divider type caused by recent
        changes to how we round clock rates.  This affects many clock drivers
        that use this common code.
        Finally there are fixes for drivers that improperly compared struct
        clk pointers (drivers must not deref these pointers).  While some of
        these drivers have done this for a long time, this did not cause a
        problem until we started generating unique struct clk pointers for
        every consumer.  A new function, clk_is_match was introduced to get
        these drivers working again and they are fixed up to no longer deref
        the pointers themselves"
      * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
        ASoC: kirkwood: fix struct clk pointer comparing
        ASoC: fsl_spdif: fix struct clk pointer comparing
        ARM: imx: fix struct clk pointer comparing
        clk: introduce clk_is_match
        clk: don't export static symbol
        clk: divider: fix calculation of initial best divider when rounding to closest
        clk: divider: fix selection of divider when rounding to closest
        clk: divider: fix calculation of maximal parent rate for a given divider
        clk: divider: return real rate instead of divider value
        clk: qcom: fix platform_no_drv_owner.cocci warnings
        clk: qcom: fix platform_no_drv_owner.cocci warnings
        clk: qcom: Add PLL4 vote clock
        clk: qcom: lcc-msm8960: Fix PLL rate detection
        clk: qcom: Fix slimbus n and m val offsets
        clk: ti: Fix FAPLL parent enable bit handling