1. 24 Dec, 2010 4 commits
  2. 23 Dec, 2010 2 commits
  3. 22 Dec, 2010 31 commits
  4. 21 Dec, 2010 3 commits
    • Santosh Shilimkar's avatar
      OMAP4: clock data: Keep L3INSTR clock domain modulemode under HW control · 60a0e5d9
      Santosh Shilimkar authored
      
      
      L3INSTR clock domain is read only register and its reset value is
      HW_AUTO. The modules withing this clock domain needs to be kept under
      hardware control.
      
      MODULEMODE:
      - 0x0: Module is disable by software. Any INTRCONN access to module
        results in an error, except if resulting from a module wakeup
        (asynchronous wakeup).
      - 0x1: Module is managed automatically by hardware according to
        clock domain transition. A clock domain sleep transition put
        module into idle. A wakeup domain transition put it back
        into function. If CLKTRCTRL=3, any INTRCONN access to module
        is always granted. Module clocks may be gated according to
        the clock domain state.
      
      This patch keeps CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL
      and CM_L3INSTR_INTRCONN_WP1_CLKCTRL module mode under hardware control
      by using ENABLE_ON_INIT flag.
      
      Without this the OMAP4 device OFF mode SAR restore phase aborts during
      interconnect register restore phase. This can be also handled by doing
      explicit a clock enable and disable in the low power code since there
      is no direct module associated with it. But that seems not necessary
      since the clock domain is under HW control.
      Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      Acked-by: default avatarBenoit Cousson <b-cousson@ti.com>
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      60a0e5d9
    • Santosh Shilimkar's avatar
      OMAP4: powerdomain: Remove L3INIT_PD OFF state · 80f09365
      Santosh Shilimkar authored
      
      
      On OMAP4, there is an issue when L3INIT transitions to OFF mode without
      device OFF. The SAR restore mechanism will not get triggered without
      wakeup from device OFF and hence the USB host and USB TLL context
      will not be restored.
      
      Hardware team recommended to remove the OFF state support for L3INIT_PD
      since there is no power impact. It will be removed on next OMAP revision
      (OMAP4440 and beyond).
      
      Hence this patch removed the OFF state from L3INIT_PD. The deepest
      state supported on L3INIT_PD is OSWR just like CORE_PD and PER_PD
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      [b-cousson@ti.com: update the changelog with next OMAP info]
      Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      80f09365
    • Rajendra Nayak's avatar
      OMAP4: powerdomain: l4per pwrdm does not support OFF · 474e7aeb
      Rajendra Nayak authored
      
      
      The l4per power domain in ES2.0 does support only RET and ON states.
      The previous ES1.0 HW database was wrong and thus fixed on ES2.
      Change the pwrsts field to reflect that.
      Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
      Acked-by: default avatarBenoit Cousson <b-cousson@ti.com>
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      474e7aeb