1. 08 Oct, 2014 1 commit
  2. 25 Sep, 2014 6 commits
  3. 24 Sep, 2014 7 commits
    • Olof Johansson's avatar
      drivers/soc: ti: fix build break with modules · b2fc3f3c
      Olof Johansson authored
      
      
      Fixes below build break by not switching to stubs when the driver is a module:
      
      drivers/soc/ti/knav_dma.c:418:7: error: redefinition of 'knav_dma_open_channel'
       void *knav_dma_open_channel(struct device *dev, const char *name,
             ^
      In file included from drivers/soc/ti/knav_dma.c:26:0:
      include/linux/soc/ti/knav_dma.h:165:21: note: previous definition of 'knav_dma_open_channel' was here
       static inline void *knav_dma_open_channel(struct device *dev, const char *name,
                           ^
      
      Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      b2fc3f3c
    • Olof Johansson's avatar
      Merge tag 'drivers-soc-ti-v2' of... · 37309643
      Olof Johansson authored
      Merge tag 'drivers-soc-ti-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
      
      Merge "soc: Keystone SOC Navigator drivers for 3.18" from Santosh Shilimkar:
      
      Keystone SOC Navigator drivers for 3.18
      
      The Keystone Multi-core Navigator contains QMSS and packet DMA
      subsystems which interwork together to form the Navigator cloud
      used by various subsystems like NetCP, SRIO, SideBand Crypto
      engines etc.
      
      * tag 'drivers-soc-ti-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone
      
      :
        MAINTAINERS: Add Keystone Multicore Navigator drivers entry
        soc: ti: add Keystone Navigator DMA support
        Documentation: dt: soc: add Keystone Navigator DMA bindings
        soc: ti: add Keystone Navigator QMSS driver
        Documentation: dt: soc: add Keystone Navigator QMSS bindings
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      37309643
    • Santosh Shilimkar's avatar
    • Santosh Shilimkar's avatar
      soc: ti: add Keystone Navigator DMA support · 88139ed0
      Santosh Shilimkar authored
      The Keystone Navigator DMA driver sets up the dma channels and flows for
      the QMSS(Queue Manager SubSystem) who triggers the actual data movements
      across clients using destination queues. Every client modules like
      NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
      Engines has its own instance of packet dma hardware. QMSS has also
      an internal packet DMA module which is used as an infrastructure
      DMA with zero copy.
      
      Initially this driver was proposed as DMA engine driver but since the
      hardware is not typical DMA engine and hence doesn't comply with typical
      DMA engine driver needs, that approach was naked. Link to that
      discussion -
      	https://lkml.org/lkml/2014/3/18/340
      
      
      
      As aligned, now we pair the Navigator DMA with its companion Navigator
      QMSS subsystem driver.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Olof Johansson <olof@lixom.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSandeep Nair <sandeep_n@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      88139ed0
    • Santosh Shilimkar's avatar
      Documentation: dt: soc: add Keystone Navigator DMA bindings · 8172296d
      Santosh Shilimkar authored
      The Keystone Navigator DMA driver sets up the dma channels and flows for
      the QMSS(Queue Manager SubSystem) who triggers the actual data movements
      across clients using destination queues. Every client modules like
      NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
      Engines has its own instance of packet dma hardware. QMSS has also
      an internal packet DMA module which is used as an infrastructure
      DMA with zero copy.
      
      Initially this driver was proposed as DMA engine driver but since the
      hardware is not typical DMA engine and hence doesn't comply with typical
      DMA engine driver needs, that approach was naked. Link to that
      discussion -
      	https://lkml.org/lkml/2014/3/18/340
      
      
      
      As aligned, now we pair the Navigator DMA with its companion Navigator
      QMSS subsystem driver.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Olof Johansson <olof@lixom.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSandeep Nair <sandeep_n@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      8172296d
    • Sandeep Nair's avatar
      soc: ti: add Keystone Navigator QMSS driver · 41f93af9
      Sandeep Nair authored
      
      
      The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
      the main hardware sub system which forms the backbone of the Keystone
      Multi-core Navigator. QMSS consist of queue managers, packed-data structure
      processors(PDSP), linking RAM, descriptor pools and infrastructure
      Packet DMA.
      
      The Queue Manager is a hardware module that is responsible for accelerating
      management of the packet queues. Packets are queued/de-queued by writing or
      reading descriptor address to a particular memory mapped location. The PDSPs
      perform QMSS related functions like accumulation, QoS, or event management.
      Linking RAM registers are used to link the descriptors which are stored in
      descriptor RAM. Descriptor RAM is configurable as internal or external memory.
      
      The QMSS driver manages the PDSP setups, linking RAM regions,
      queue pool management (allocation, push, pop and notify) and descriptor
      pool management. The specifics on the device tree bindings for
      QMSS can be found in:
      	Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Olof Johansson <olof@lixom.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSandeep Nair <sandeep_n@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      41f93af9
    • Sandeep Nair's avatar
      Documentation: dt: soc: add Keystone Navigator QMSS bindings · a4dfb8c4
      Sandeep Nair authored
      
      
      The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
      the main hardware sub system which forms the backbone of the Keystone
      Multi-core Navigator. QMSS consist of queue managers, packed-data structure
      processors(PDSP), linking RAM, descriptor pools and infrastructure
      Packet DMA.
      
      The Queue Manager is a hardware module that is responsible for accelerating
      management of the packet queues. Packets are queued/de-queued by writing or
      reading descriptor address to a particular memory mapped location. The PDSPs
      perform QMSS related functions like accumulation, QoS, or event management.
      Linking RAM registers are used to link the descriptors which are stored in
      descriptor RAM. Descriptor RAM is configurable as internal or external memory.
      
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Olof Johansson <olof@lixom.net>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSandeep Nair <sandeep_n@ti.com>
      Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
      a4dfb8c4
  4. 23 Sep, 2014 3 commits
    • Olof Johansson's avatar
      Merge tag 'mailbox-for-v3.18' of... · 791cc88c
      Olof Johansson authored
      Merge tag 'mailbox-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
      
      Mailbox related changes for omaps to get it to work with
      device tree.
      
      * tag 'mailbox-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
      
      :
        mailbox/omap: add support for parsing dt devices
        Documentation: dt: add omap mailbox bindings
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      791cc88c
    • Olof Johansson's avatar
      Merge tag 'intc-for-v3.18' of... · 9cdf6bd5
      Olof Johansson authored
      Merge tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
      
      Merge "omap intc changes for v3.18 merge window" from Tony Lindgren:
      
      Interrupt code related clean-up for omap2 and 3 to make
      it ready to move to drivers/irqchip. Note that this series
      does not yet move the interrupt code to drivers, that will
      be posted separately as a follow-up series.
      
      Note that this branch has a dependency to patches both
      in fixes-v3.18-not-urgent and soc-for-v3.18 and is based on
      a merge. Without doing the merge, off-idle would not work
      properly for git bisect.
      
      * tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap
      
      : (325 commits)
        arm: omap: intc: switch over to linear irq domain
        arm: omap: irq: get rid of ifdef hack
        arm: omap: irq: introduce omap_nr_pending
        arm: omap: irq: remove nr_irqs argument
        arm: omap: irq: remove unnecessary header
        arm: omap: irq: drop omap2_intc_handle_irq()
        arm: omap: irq: drop omap3_intc_handle_irq()
        arm: omap: irq: call set_handle_irq() from .init_irq
        arm: omap: irq: move some more code around
        arm: boot: dts: omap2/3/am33xx: drop ti,intc-size
        arm: omap: irq: drop ti,intc-size support
        arm: boot: dts: am33xx/omap3: fix intc compatible flag
        arm: omap: irq: use compatible flag to figure out number of IRQ lines
        arm: omap: irq: add specific compatibles for omap3 and am33xx devices
        arm: omap: irq: drop .handle_irq and .init_irq fields
        arm: omap: irq: use IRQCHIP_DECLARE macro
        arm: omap: irq: call set_handle_irq() from intc_of_init
        arm: omap: irq: make intc_of_init static
        arm: omap: irq: reorganize code a little bit
        arm: omap: irq: always define omap3 support
        ...
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      9cdf6bd5
    • Olof Johansson's avatar
      Merge tag 'at91-drivers2' of git://github.com/at91linux/linux-at91 into next/drivers · 4693c723
      Olof Johansson authored
      Merge " Second drivers series for AT91/3.18" from Nicolas Ferre:
      
      - move of the PIT (basic timer) from mach-at91 to its proper location:
        drivers/clocksource
      - big cleanup of this driver along the way
      
      * tag 'at91-drivers2' of git://github.com/at91linux/linux-at91
      
      :
        ARM: at91: PIT: Move the driver to drivers/clocksource
        ARM: at91: Give the PIT irq as an argument of at91sam926x_pit_init
        ARM: at91: Convert the boards to the init_time callback
        ARM: at91: soc: Add init_time callback
        ARM: at91: PIT: (Almost) remove the global variables
        ARM: at91: PIT: use request_irq instead of setup_irq
        ARM: at91: PIT: Use pr_fmt
        ARM: at91: PIT: Use consistent exit path in probe
        ARM: at91: dt: Remove init_time definitions
        ARM: at91: PIT: Rework probe functions
        ARM: at91: PIT: Use of_have_populated_dt instead of CONFIG_OF
        ARM: at91: PIT: Use DIV_ROUND_CLOSEST to compute the cycles
        ARM: at91: generic.h: Add include safe guards
        ARM: at91: PIT: Follow the general coding rules
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      4693c723
  5. 19 Sep, 2014 2 commits
  6. 16 Sep, 2014 10 commits
  7. 15 Sep, 2014 2 commits
  8. 11 Sep, 2014 9 commits