- 26 Aug, 2011 1 commit
-
-
Feng Tang authored
Those info will be used when spi controller driver setup max3110 as a slave device Signed-off-by:
Feng Tang <feng.tang@intel.com> Signed-off-by:
Alan Cox <alan@linux.intel.com> Signed-off-by:
Dirk Brandewie <dirk.brandewie@gmail.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de>
-
- 07 May, 2011 1 commit
-
-
Luis R. Rodriguez authored
Fix these Sparse complaints: CHECK arch/x86/platform/mrst/mrst.c arch/x86/platform/mrst/mrst.c:197:13: warning: symbol 'mrst_time_init' was not declared. Should it be static? arch/x86/platform/mrst/mrst.c:219:16: warning: symbol 'mrst_arch_setup' was not declared. Should it be static? Acked-by:
Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Roman Gezikov <roman.gezikov@atheros.com> Cc: Joonas Viskari <joonas.viskari@atheros.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Allen Kao <allen.kao@atheros.com> Signed-off-by:
Luis R. Rodriguez <lrodriguez@atheros.com> Link: http://lkml.kernel.org/r/1304719209-26913-1-git-send-email-lrodriguez@atheros.comSigned-off-by:
Ingo Molnar <mingo@elte.hu>
-
- 12 Apr, 2011 1 commit
-
-
Jacob Pan authored
Moorestown systems crash on boot because the secondary CPU clockevent (apbt1) will fail to request irq#1, which does not have ioapic chip in its irq_desc[] entry. Background: Moorestown platform does not have ISA bus nor legacy IRQs. It reuses the range of legacy IRQs for regular device interrupts. The routing information of early system device IRQs (timers) are obtained from firmware provided SFI tables. We reuse/fake MP configuration table to facilitate IRQ setup with IOAPIC. Maintaining a 1:1 mapping of IOAPIC pin (RTE entry) and IRQ# makes routing information clean and easy to understand on Moorestown. Though optional. This patch allows SFI timer and vRTC IRQ to be treated as ISA IRQ so that pin2irq mapping will be 1:1. Also fixed MP table type and use macros to clearly set MP IRQ entries. As a result, apbt timer and RTC interrupts on Moorestown are within legacy IRQ range: # cat /proc/interrupts CPU0 CPU1 0: 11249 0 IO-APIC-edge apbt0 1: 0 12271 IO-APIC-edge apbt1 8: 887 0 IO-APIC-fasteoi dw_spi 13: 0 0 IO-APIC-fasteoi INTEL_MID_DMAC2 14: 0 0 IO-APIC-fasteoi rtc0 Further discussion of this patch can be found at: https://lkml.org/lkml/2010/6/10/70Suggested-by:"Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by:
Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Feng Tang <feng.tang@intel.com> Cc: Alan Cox <alan@linux.intel.com> Cc: Arjan van de Ven <arjan@linux.intel.com> Link: http://lkml.kernel.org/r/1302286980-21139-1-git-send-email-jacob.jun.pan@linux.intel.comSigned-off-by:
-
- 14 Feb, 2011 1 commit
-
-
Feng Tang authored
If we don't assign Moorestown specific wallclock init and ops function the rtc/persisent clock code will use cmos rtc for access, this will crash Moorestown in that the ioports are not present. Also in vrtc driver, should avoid using cmos access to check UIP status. [feng.tang@intel.com: use set_fixmap_offset_nocache() to simplify code] Signed-off-by:
Thomas Gleixner <tglx@linutronix.de>
-
- 09 Dec, 2010 1 commit
-
-
Feng Tang authored
There are 3 places defining similar functions of saving IRQ vector info into mp_irqs[] array: mmparse/acpi/mrst. Replace the redundant code by a common function in io_apic.c as it's only called when CONFIG_X86_IO_APIC=y Signed-off-by:
-
- 11 Nov, 2010 4 commits
-
-
Feng Tang authored
When setting up the mpc_intsrc structure for vRTC's IRQ, we need to set its irqflag to level trigger, otherwise it will be taken as edge triggered and the vRTC IRQ will fire only once, as there is never a EOI issued from the IA core for it. The original code worked in previous kernel. This is because it was configured to level trigger type by luck. It fell into the default PCI trigger category which is level triggered. Signed-off-by:
-
Vinod Koul authored
This patch adds the sound card bindings for Moorestown (pmic_audio) and the Medfield platform (msic_audio) as IPC devices. This ensures they will be created at the right time. Signed-off-by:
Vinod Koul <vinod.koul@intel.com> Signed-off-by:
-
Feng Tang authored
Moorestown platform doesn't have a m146818 RTC device like traditional x86 PC, but a firmware emulated virtual RTC device(vrtc), which provides some basic RTC functions like get/set time. vrtc serves as the only wall clock device on Moorestown platform. [ tglx: Changed the exports to _GPL ] Signed-off-by:
-
Alek Du authored
Moorestowns needs to use a special IPC command to reboot or shutdown the platform. Signed-off-by:
Alek Du <alek.du@intel.com> Signed-off-by:
-
- 09 Nov, 2010 2 commits
-
-
Jacob Pan authored
Penwell has APB timer based watchdog timers, it requires platform code to parse SFI MTMR tables in order to claim its timer. This patch will always parse SFI MTMR regardless of system timer configuration choices. Otherwise, SFI MTMR table may not get parsed if running on Medfield with always-on local APIC timers and constant TSC. Watchdog timer driver will then not get a timer to use. Signed-off-by:
-
Feng Tang authored
SFI provides a series of tables. These describe the platform devices present including SPI and I²C devices, as well as various sensors, keypads and other glue as well as interfaces provided via the SCU IPC mechanism (intel_scu_ipc.c) This patch is a merge of the core elements and relevant fixes from the Intel development code by Feng, Alek, myself into a single coherent patch for upstream submission. It provides the needed infrastructure to register I2C, SPI and platform devices described by the tables, as well as handlers for some of the hardware already supported in kernel. The 0.8 firmware also provides GPIO tables. Devices are created at boot time or if they are SCU dependant at the point an SCU is discovered. The existing Linux device mechanisms will then handle the device binding. At an abstract level this is an SFI to Linux device translator. Device/platform specific setup/glue is in this file. This is done so that the drivers for the generic I²C and SPI bus devices remain cross platform as they should. (Updated from RFC version to correct the emc1403 name used by the firmware and a wrongly used #define) Signed-off-by:
Alek Du <alek.du@linux.intel.com> LKML-Reference: <20101109112158.20013.6158.stgit@localhost.localdomain> [Clean ups, removal of 0.7 support] Signed-off-by:
Feng Tang <feng.tang@linux.intel.com> [Clean ups] Signed-off-by:
-
- 27 Oct, 2010 1 commit
-
-
Thomas Gleixner authored
Signed-off-by:
-
- 07 Jul, 2010 1 commit
-
-
Feng Tang authored
It will just return 0 as there is no i8042 controller Signed-off-by:
Dmitry Torokhov <dtor@mail.ru> Signed-off-by:
H. Peter Anvin <hpa@linux.intel.com>
-
- 19 May, 2010 4 commits
-
-
H. Peter Anvin authored
We have an enum mrst_timer_options, use it so that the kernel knows if we're missing something from a switch statement or equivalent. Signed-off-by: -
H. Peter Anvin authored
We have an enum, might as well use it. While we're at it, make it an inline... there is really no point in calling a function for this stuff. LKML-Reference: <1274295685-6774-3-git-send-email-jacob.jun.pan@linux.intel.com> Signed-off-by:
-
Jacob Pan authored
Always-on local APIC timer (ARAT) has been introduced to Medfield, along with the platform APB timers we have more timer configuration options between Moorestown and Medfield. This patch adds run-time detection of avaiable timer features so that we can treat Medfield as a variant of Moorestown and set up the optimal timer options for each platform. i.e. Medfield: per cpu always-on local APIC timer Moorestown: per cpu APB timer Manual override is possible via cmdline option x86_mrst_timer. Signed-off-by:
-
Jacob Pan authored
Medfield is the follow-up of Moorestown, it is treated under the same HW sub-architecture. However, we do need to know the CPU type in order for some of the driver to act accordingly. We also have different optimal clock configuration for each CPU type. Signed-off-by:
-
- 16 May, 2010 1 commit
-
-
Jacob Pan authored
Moorestown does not have BIOS provided MP tables, we can save some time by avoiding scaning of these tables. e.g. [ 0.000000] Scan SMP from c0000000 for 1024 bytes. [ 0.000000] Scan SMP from c009fc00 for 1024 bytes. [ 0.000000] Scan SMP from c00f0000 for 65536 bytes. [ 0.000000] Scan SMP from c00bfff0 for 1024 bytes. Searching EBDA with the base at 0x40E will also result in random pointer deferencing within 1MB. This can be a problem in Lincroft if the pointer hits VGA area and VGA mode is not enabled. Signed-off-by:
-
- 24 Feb, 2010 5 commits
-
-
Jacob Pan authored
Add Moorestown platform clock setup code to the x86_init abstraction. Signed-off-by:
Jacob Pan <jacob.jun.pan@intel.com> LKML-Reference: <43F901BD926A4E43B106BF17856F0755A318D2D4@orsmsx508.amr.corp.intel.com> Signed-off-by:
H. Peter Anvin <hpa@zytor.com>
-
Feng Tang authored
vRTC information is obtained from SFI tables on Moorestown, this patch parses these tables and assign the information. Signed-off-by:
-
Jacob Pan authored
Moorestown platform timer information is obtained from SFI FW tables. This patch parses SFI table then assign the irq information to mp_irqs. Signed-off-by:
-
Jacob Pan authored
This patch added Moorestown platform specific PCI init functions. Signed-off-by:
-
Jacob Pan authored
Moorestown has no legacy PIC; point it to the null legacy PIC. Signed-off-by:
-
- 31 Aug, 2009 1 commit
-
-
Thomas Gleixner authored
Moorestown MID devices need to be detected early in the boot process to setup and do not call x86_default_early_setup as there is no EBDA region to reserve. [ Copied the minimal code from Jacobs latest MRST series ] Signed-off-by:
-
