1. 27 Feb, 2012 1 commit
  2. 23 Jan, 2012 2 commits
  3. 23 Dec, 2011 1 commit
    • Dave Martin's avatar
      ARM: 7197/1: errata: Remove SMP dependency for erratum 751472 · ba90c516
      Dave Martin authored
      
      
      Activation conditions for a workaround should not be encoded in the
      workaround's direct dependencies if this makes otherwise reasonable
      configuration choices impossible.
      
      This patches uses the SMP/UP patching facilities instead to compile
      out the workaround if the configuration means that it is definitely
      not needed.
      
      This means that configs for buggy silicon can simply select
      ARM_ERRATA_751472, without preventing a UP kernel from being built
      or duplicatiing knowledge about when to activate the workaround.
      This seems the correct way to do things, because the erratum is a
      property of the silicon, irrespective of what the kernel config
      happens to be.
      Signed-off-by: default avatarDave Martin <dave.martin@linaro.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ba90c516
  4. 11 Dec, 2011 1 commit
  5. 08 Dec, 2011 2 commits
  6. 06 Dec, 2011 1 commit
  7. 01 Oct, 2011 1 commit
  8. 20 Sep, 2011 3 commits
  9. 28 Aug, 2011 3 commits
  10. 21 Jul, 2011 1 commit
  11. 07 Jul, 2011 5 commits
  12. 24 Jun, 2011 2 commits
  13. 09 Jun, 2011 1 commit
    • Russell King's avatar
      Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID" · 07989b7a
      Russell King authored
      This reverts commit 52af9c6c.
      
      Will Deacon reports that:
      
       In 52af9c6c
      
       ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID")
       I updated the ASID rollover code to use only the kernel page tables
       whilst updating the ASID.
      
       Unfortunately, the code to restore the user page tables was part of a
       later patch which isn't yet in mainline, so this leaves the code
       quite broken.
      
      We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW
      from ARM, so lets revert these until we can properly sort out what we're
      doing with the ARM context switching.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      07989b7a
  14. 26 May, 2011 2 commits
  15. 02 Apr, 2011 1 commit
  16. 31 Mar, 2011 1 commit
  17. 09 Mar, 2011 1 commit
  18. 22 Feb, 2011 1 commit
  19. 19 Feb, 2011 1 commit
  20. 14 Jan, 2011 1 commit
  21. 22 Dec, 2010 3 commits
  22. 30 Nov, 2010 1 commit
    • Dave Martin's avatar
      ARM: 6501/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in mm/proc-v7.S · 6323875d
      Dave Martin authored
      
      
      Directives such as .long and .word do not magically cause the
      assembler location counter to become aligned in gas.  As a result,
      using these directives in code sections can result in misaligned
      data words when building a Thumb-2 kernel (CONFIG_THUMB2_KERNEL).
      
      This is a Bad Thing, since the ABI permits the compiler to assume
      that fundamental types of word size or above are word- aligned when
      accessing them from C.  If the data is not really word-aligned,
      this can cause impaired performance and stray alignment faults in
      some circumstances.
      
      In general, the following rules should be applied when using data
      word declaration directives inside code sections:
      
          * .quad and .double:
               .align 3
      
          * .long, .word, .single, .float:
               .align (or .align 2)
      
          * .short:
              No explicit alignment required, since Thumb-2
              instructions are always 2 or 4 bytes in size.
              immediately after an instruction.
      
      In this specific case, we can achieve the desired alignment by
      forcing a 32-bit branch instruction using the W() macro, since the
      assembler location counter is already 32-bit aligned in this case.
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarDave Martin <dave.martin@linaro.org>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      6323875d
  23. 04 Nov, 2010 2 commits
    • Leif Lindholm's avatar
      ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processors · 64d2dc38
      Leif Lindholm authored
      
      
      The SWP instruction was deprecated in the ARMv6 architecture,
      superseded by the LDREX/STREX family of instructions for
      load-linked/store-conditional operations. The ARMv7 multiprocessing
      extensions mandate that SWP/SWPB instructions are treated as undefined
      from reset, with the ability to enable them through the System Control
      Register SW bit.
      
      This patch adds the alternative solution to emulate the SWP and SWPB
      instructions using LDREX/STREX sequences, and log statistics to
      /proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also
      modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when
      user RO.
      Signed-off-by: default avatarLeif Lindholm <leif.lindholm@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarKirill A. Shutemov <kirill@shutemov.name>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      64d2dc38
    • Catalin Marinas's avatar
      ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUs · 247055aa
      Catalin Marinas authored
      
      
      This patch removes the domain switching functionality via the set_fs and
      __switch_to functions on cores that have a TLS register.
      
      Currently, the ioremap and vmalloc areas share the same level 1 page
      tables and therefore have the same domain (DOMAIN_KERNEL). When the
      kernel domain is modified from Client to Manager (via the __set_fs or in
      the __switch_to function), the XN (eXecute Never) bit is overridden and
      newer CPUs can speculatively prefetch the ioremap'ed memory.
      
      Linux performs the kernel domain switching to allow user-specific
      functions (copy_to/from_user, get/put_user etc.) to access kernel
      memory. In order for these functions to work with the kernel domain set
      to Client, the patch modifies the LDRT/STRT and related instructions to
      the LDR/STR ones.
      
      The user pages access rights are also modified for kernel read-only
      access rather than read/write so that the copy-on-write mechanism still
      works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register
      (CPU_32v6K is defined) since writing the TLS value to the high vectors page
      isn't possible.
      
      The user addresses passed to the kernel are checked by the access_ok()
      function so that they do not point to the kernel space.
      Tested-by: default avatarAnton Vorontsov <cbouatmailru@gmail.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      247055aa
  24. 08 Oct, 2010 2 commits
    • Russell King's avatar
      ARM: hotplug cpu: Keep processor information, startup code & __lookup_processor_type · 5085f3ff
      Russell King authored
      
      
      When hotplug CPU is enabled, we need to keep the list of supported CPUs,
      their setup functions, and __lookup_processor_type in place so that we
      can find and initialize secondary CPUs.  Move these into the __CPUINIT
      section.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      5085f3ff
    • Tony Lindgren's avatar
      ARM: 6435/1: Fix HWCAP_TLS flag for ARM11MPCore/Cortex-A9 · c0bb5862
      Tony Lindgren authored
      Commit 14eff181
      
       added proper
      detection for ARM11MPCore/Cortex-A9 instead of detecting them
      as ARMv7. However, it was missing the HWCAP_TLS flags.
      
      HWCAP_TLS is needed if support for earlier ARMv6 is compiled
      into the same kernel. Without HWCAP_TLS flags the userspace
      won't work unless nosmp is specified:
      
      Kernel panic - not syncing: Attempted to kill init!
      CPU0: stopping
      <c005d5e4>] (unwind_backtrace+0x0/0xec) from [<c004c2f8>] (do_IPI+0xfc/0x184)
      <c004c2f8>] (do_IPI+0xfc/0x184) from [<c03f25bc>] (__irq_svc+0x9c/0x160)
      Exception stack(0xc0565f80 to 0xc0565fc8)
      5f80: 00000001 c05772a0 00000000 00003a61 c0564000 c05cf500 c003603c c0578600
      5fa0: 80033ef0 410fc091 0000001f 00000000 00000000 c0565fc8 c00b91f8 c0057cb4
      5fc0: 20000013 ffffffff
      [<c03f25bc>] (__irq_svc+0x9c/0x160) from [<c0057cb4>] (default_idle+0x30/0x38)
      [<c0057cb4>] (default_idle+0x30/0x38) from [<c005829c>] (cpu_idle+0x9c/0xf8)
      [<c005829c>] (cpu_idle+0x9c/0xf8) from [<c0008d48>] (start_kernel+0x2a4/0x300)
      [<c0008d48>] (start_kernel+0x2a4/0x300) from [<80008084>] (0x80008084)
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      c0bb5862