1. 26 Feb, 2007 3 commits
  2. 16 Feb, 2007 1 commit
  3. 13 Feb, 2007 1 commit
    • Benjamin Romer's avatar
      [PATCH] x86-64: update IO-APIC dest field to 8-bit for xAPIC · ee4eff6f
      Benjamin Romer authored
      On the Unisys ES7000/ONE system, we encountered a problem where performing
      a kexec reboot or dump on any cell other than cell 0 causes the system
      timer to stop working, resulting in a hang during timer calibration in the
      new kernel.
      
      We traced the problem to one line of code in disable_IO_APIC(), which needs
      to restore the timer's IO-APIC configuration before rebooting.  The code is
      currently using the 4-bit physical destination field, rather than using the
      8-bit logical destination field, and it cuts off the upper 4 bits of the
      timer's APIC ID.  If we change this to use the logical destination field,
      the timer works and we can kexec on the upper cells.  This was tested on
      two different cells (0 and 2) in an ES7000/ONE system.
      
      For reference, the relevant Intel xAPIC spec is kept at
      ftp://download.intel.com/design/chipsets/e8501/datashts/30962001.pdf
      
      ,
      specifically on page 334.
      Signed-off-by: default avatarBenjamin M Romer <benjamin.romer@unisys.com>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Cc: Andi Kleen <ak@suse.de>
      Cc: "Eric W. Biederman" <ebiederm@xmission.com>
      Cc: Vivek Goyal <vgoyal@in.ibm.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      ee4eff6f
  4. 07 Feb, 2007 1 commit
  5. 08 Jan, 2007 1 commit
  6. 06 Dec, 2006 4 commits
  7. 28 Nov, 2006 1 commit
  8. 15 Nov, 2006 1 commit
    • Eric W. Biederman's avatar
      [PATCH] Use delayed disable mode of ioapic edge triggered interrupts · 45c99533
      Eric W. Biederman authored
      
      
      Komuro reports that ISA interrupts do not work after a disable_irq(),
      causing some PCMCIA drivers to not work, with messages like
      
      	eth0: Asix AX88190: io 0x300, irq 3, hw_addr xx:xx:xx:xx:xx:xx
      	eth0: found link beat
      	eth0: autonegotiation complete: 100baseT-FD selected
      	eth0: interrupt(s) dropped!
      	eth0: interrupt(s) dropped!
      	eth0: interrupt(s) dropped!
      	...
      
      Linus Torvalds <torvalds@osdl.org> said:
      
        "Now, edge-triggered interrupts are a _lot_ harder to mask, because the
         Intel APIC is an unbelievable piece of sh*t, and has the edge-detect logic
         _before_ the mask logic, so if a edge happens _while_ the device is
         masked, you'll never ever see the edge ever again (unmasking will not
         cause a new edge, so you simply lost the interrupt).
      
         So when you "mask" an edge-triggered IRQ, you can't really mask it at all,
         because if you did that, you'd lose it forever if the IRQ comes in while
         you masked it. Instead, we're supposed to leave it active, and set a flag,
         and IF the IRQ comes in, we just remember it, and mask it at that point
         instead, and then on unmasking, we have to replay it by sending a
         self-IPI."
      
      This trivial patch solves the problem.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@redhat.com>
      Acked-by: default avatarKomuro <komurojun-mbn@nifty.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      45c99533
  9. 08 Nov, 2006 3 commits
  10. 24 Oct, 2006 2 commits
    • Eric W. Biederman's avatar
      [PATCH] x86-64: Only look at per_cpu data for online cpus. · 70a0a535
      Eric W. Biederman authored
      
      
      When I generalized __assign_irq_vector I failed to pay attention
      to what happens when you access a per cpu data structure for
      a cpu that is not online.   It is an undefined case making any
      code that does it have undefined behavior as well.
      
      The code still needs to be able to allocate a vector across cpus
      that are not online to properly handle combinations like lowest
      priority interrupt delivery and cpu_hotplug.  Not that we can do
      that today but the infrastructure shouldn't prevent it.
      
      So this patch updates the places where we touch per cpu data
      to only touch online cpus, it makes cpu vector allocation
      an atomic operation with respect to cpu hotplug, and it updates
      the cpu start code to properly initialize vector_irq so we
      don't have inconsistencies.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      70a0a535
    • Eric W. Biederman's avatar
      [PATCH] x86-64: Simplify the vector allocator. · d1752aa8
      Eric W. Biederman authored
      
      
      There is no reason to remember a per cpu position of which vector
      to try.  Keeping a global position is simpler and more likely to
      result in a global vector allocation even if I don't need or require
      it.  For level triggered interrupts this means we are less likely to
      acknowledge another cpus irq, and cause the level triggered irq to
      harmlessly refire.
      
      This simplification makes it easier to only access data structures
      of  online cpus, by having fewer special cases to deal with.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      d1752aa8
  11. 21 Oct, 2006 3 commits
  12. 17 Oct, 2006 1 commit
  13. 12 Oct, 2006 1 commit
  14. 11 Oct, 2006 1 commit
  15. 08 Oct, 2006 2 commits
    • Eric W. Biederman's avatar
      [PATCH] x86_64 irq: Allocate a vector across all cpus for genapic_flat. · c7111c13
      Eric W. Biederman authored
      
      
      The problem we can't take advantage of lowest priority delivery mode if
      the vectors are allocated for only one cpu at a time.  Nor can we work
      around hardware that assumes lowest priority delivery mode is always
      used with several cpus.
      
      So this patch introduces the concept of a vector_allocation_domain.  A
      set of cpus that will receive an irq on the same vector.  Currently the
      code for implementing this is placed in the genapic structure so we can
      vary this depending on how we are using the io_apics.
      
      This allows us to restore the previous behaviour of genapic_flat without
      removing the benefits of having separate vector allocation for large
      machines.
      
      This should also fix the problem report where a hyperthreaded cpu was
      receving the irq on the wrong hyperthread when in logical delivery mode
      because the previous behaviour is restored.
      
      This patch properly records our allocation of the first 16 irqs to the
      first 16 available vectors on all cpus.  This should be fine but it may
      run into problems with multiple interrupts at the same interrupt level.
      Except for some badly maintained comments in the code and the behaviour
      of the interrupt allocator I have no real understanding of that problem.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Acked-by: default avatarMuli Ben-Yehuda <muli@il.ibm.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      c7111c13
    • Eric W. Biederman's avatar
      [PATCH] i386/x86_64: Remove global IO_APIC_VECTOR · b940d22d
      Eric W. Biederman authored
      
      
      Which vector an irq is assigned to now varies dynamically and is
      not needed outside of io_apic.c.  So remove the possibility
      of accessing the information outside of io_apic.c and remove
      the silly macro that makes looking for users of irq_vector
      difficult.
      
      The fact this compiles ensures there aren't any more pieces
      of the old CONFIG_PCI_MSI weirdness that I failed to remove.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      b940d22d
  16. 04 Oct, 2006 12 commits
    • Eric W. Biederman's avatar
      [PATCH] htirq: tidy up the htirq code · 95d77884
      Eric W. Biederman authored
      
      
      This moves the declarations for the architecture helpers into
      include/linux/htirq.h from the generic include/linux/pci.h.  Hopefully this
      will make this distinction clearer.
      
      htirq.h is included where it is needed.
      
      The dependency on the msi code is fixed and removed.
      
      The Makefile is tidied up.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      95d77884
    • Eric W. Biederman's avatar
      [PATCH] msi: refactor and move the msi irq_chip into the arch code · 3b7d1921
      Eric W. Biederman authored
      
      
      It turns out msi_ops was simply not enough to abstract the architecture
      specific details of msi.  So I have moved the resposibility of constructing
      the struct irq_chip to the architectures, and have two architecture specific
      functions arch_setup_msi_irq, and arch_teardown_msi_irq.
      
      For simple architectures those functions can do all of the work.  For
      architectures with platform dependencies they can call into the appropriate
      platform code.
      
      With this msi.c is finally free of assuming you have an apic, and this
      actually takes less code.
      
      The helpers for the architecture specific code are declared in the linux/msi.h
      to keep them separate from the msi functions used by drivers in linux/pci.h
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      3b7d1921
    • Eric W. Biederman's avatar
      [PATCH] Initial generic hypertransport interrupt support · 8b955b0d
      Eric W. Biederman authored
      
      
      This patch implements two functions ht_create_irq and ht_destroy_irq for
      use by drivers.  Several other functions are implemented as helpers for
      arch specific irq_chip handlers.
      
      The driver for the card I tested this on isn't yet ready to be merged.
      However this code is and hypertransport irqs are in use in a few other
      places in the kernel.  Not that any of this will get merged before 2.6.19
      
      Because the ipath-ht400 is slightly out of spec this code will need to be
      generalized to work there.
      
      I think all of the powerpc uses are for a plain interrupt controller in a
      chipset so support for native hypertransport devices is a little less
      interesting.
      
      However I think this is a half way decent model on how to separate arch
      specific and generic helper code, and I think this is a functional model of
      how to get the architecture dependencies out of the msi code.
      
      [akpm@osdl.org: Kconfig fix]
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Greg KH <greg@kroah.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      8b955b0d
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: Kill irq compression · cd1182f5
      Eric W. Biederman authored
      
      
      With more irqs in the system we don't need this.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      cd1182f5
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: Kill gsi_irq_sharing · f023d764
      Eric W. Biederman authored
      
      
      After raising the number of irqs the system supports this function is no
      longer necessary.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      f023d764
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: make vector_irq per cpu · 550f2299
      Eric W. Biederman authored
      
      
      This refactors the irq handling code to make the vectors a per cpu resource so
      the same vector number can be simultaneously used on multiple cpus for
      different irqs.
      
      This should make systems that were hitting limits on the total number of irqs
      much more livable.
      
      [akpm@osdl.org: build fix]
      [akpm@osdl.org: __target_IO_APIC_irq is unneeded on UP]
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      550f2299
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: Make the external irq handlers report their vector, not the irq number · e500f574
      Eric W. Biederman authored
      
      
      This is a small pessimization but it paves the way for making this information
      per cpu.  Which allows the the maximum number of IRQS to become NR_CPUS*224.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      e500f574
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: Remove the msi assumption that irq == vector · 04b9267b
      Eric W. Biederman authored
      
      
      This patch removes the change in behavior of the irq allocation code when
      CONFIG_PCI_MSI is defined.  Removing all instances of the assumption that irq
      == vector.
      
      create_irq is rewritten to first allocate a free irq and then to assign that
      irq a vector.
      
      assign_irq_vector is made static and the AUTO_ASSIGN case which allocates an
      vector not bound to an irq is removed.
      
      The ioapic vector methods are removed, and everything now works with irqs.
      
      The definition of NR_IRQS no longer depends on CONFIG_PCI_MSI
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      04b9267b
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: Move msi message composition into io_apic.c · 589e367f
      Eric W. Biederman authored
      
      
      This removes the hardcoded assumption that irq == vector in the msi
      composition code, and it allows the msi message composition to setup logical
      mode, or lowest priorirty delivery mode as we do for other apic interrupts,
      and with the same selection criteria.
      
      Basically this moves the problem of what is in the msi message into the
      architecture irq management code where it belongs.  Not in a generic layer
      that doesn't have enough information to compose msi messages properly.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      589e367f
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: Dynamic irq support · c4fa0bbf
      Eric W. Biederman authored
      
      
      The current implementation of create_irq() is a hack but it is the current
      hack that msi.c uses, and unfortunately the ``generic'' apic msi ops depend on
      this hack.  Thus we are this hack of assuming irq == vector until the
      depencencies in the generic irq code are removed.
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      c4fa0bbf
    • Eric W. Biederman's avatar
      [PATCH] genirq: x86_64 irq: Reenable migrating irqs to other cpus · 0be6652f
      Eric W. Biederman authored
      
      
      In the latest changes the code for migrating x86_64 irqs was dropped.  This
      reads it in a fashion that will work even if we change the vector on level
      triggered irqs when we migrate them.
      
      [akpm@osdl.org: build fix]
      Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      0be6652f
    • Ingo Molnar's avatar
      [PATCH] genirq: convert the x86_64 architecture to irq-chips · f29bd1ba
      Ingo Molnar authored
      
      
      This patch converts all the x86_64 PIC controllers layers to the new and
      simpler irq-chip interrupt handling layer.
      
      [mingo@elte.hu: The patch also enables the fasteoi handler for x86_64]
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Roland Dreier <rolandd@cisco.com>
      Cc: Andi Kleen <ak@suse.de>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      f29bd1ba
  17. 26 Sep, 2006 2 commits
    • Andi Kleen's avatar
      [PATCH] Remove APIC version/cpu capability mpparse checking/printing · f2c2cca3
      Andi Kleen authored
      
      
      ACPI went to great trouble to get the APIC version and CPU capabilities
      of different CPUs before passing them to the mpparser. But all
      that data was used was to print it out.  Actually it even faked some data
      based on the boot cpu, not on the actual CPU being booted.
      
      Remove all this code because it's not needed.
      
      Cc: len.brown@intel.com
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      f2c2cca3
    • Andi Kleen's avatar
      [PATCH] Convert x86-64 to early param · 2c8c0e6b
      Andi Kleen authored
      
      
      Instead of hackish manual parsing
      
      Requires earlier i386 patchkit, but also fixes i386 early_printk again.
      
      I removed some obsolete really early parameters which didn't do anything useful.
      Also made a few parameters that needed it early (mostly oops printing setup)
      
      Also removed one panic check that wasn't visible without
      early console anyways (the early console is now initialized after that
      panic)
      
      This cleans up a lot of code.
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      2c8c0e6b