1. 17 Jun, 2012 1 commit
  2. 14 Jun, 2012 3 commits
    • Jacob Keller's avatar
      ixgbe: Check PTP Rx timestamps via BPF filter · 1d1a79b5
      Jacob Keller authored
      
      
      This patch fixes a potential Rx timestamp deadlock that causes the Rx
      timestamping to stall indefinitely. The issue could occur when a PTP packet is
      timestamped by hardware but never reaches the Rx queue. In order to prevent a
      permanent loss of timestamping, the RXSTMP(L/H) registers have to be read to
      unlock them. (This used to only occur when a packet that was timestamped
      reached the software.) However the registers can't be read early otherwise
      there is no way to correlate them to the packet.
      
      This patch introduces a filter function which can be used to determine if a
      packet should have been timestamped. Supplied with the filter setup by the
      hwtstamp ioctl, check to make sure the PTP protocol and message type match the
      expected values. If so, then read the timestamp registers (to free them.) At
      this point check the descriptor bit, if the bit is set then we know this
      packet correlates to the timestamp stored in the RXTSTAMP registers.
      Otherwise, assume that packet was dropped by the hardware, and ignore this
      timestamp value. However, we have at least unlocked the rxtstamp registers for
      future timestamping.
      
      Due to the way the driver handles skb data, it cannot be directly accessed. In
      order to work around this, a copy of the skb data into a linear buffer is
      made. From this buffer it becomes possible to read the data correctly
      Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
      Reviewed-by: default avatarRichard Cochran <richardcochran@gmail.com>
      Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      1d1a79b5
    • Jacob Keller's avatar
      ixgbe: PTP Fix hwtstamp mode settings · c19197a7
      Jacob Keller authored
      
      
      When enabling the hwtstamp mode for Rx timestamping the V2 ptp event type
      specific modes (Delay Request and Sync) have been rolled into the V2 all event
      packet modes, in order to more accurately represent what hardware is doing.
      Hardware always timestamps the Path delay packets when a V2 mode is selected,
      regardless of what type was selected (in order to always support Path delay
      mode). However this means the user selected modes of timestamping only Sync or
      Delay Request is not truly supported. This patch correctly sets the mode for
      the hwtstamp config and returns to the user that all V2 event packets will be
      timestamped.
      Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
      Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      c19197a7
    • Jacob Keller's avatar
      ixgbe: ptp code cleanup · 0ede4a60
      Jacob Keller authored
      
      
      This patch fixes two minor nits from Richard Cochran. The first is a case of
      ambitious line wrapping that wasn't necessary. The second is to re-order the
      flag checks for PPS support. Previously, the hardware test was done first, and
      the interrupt flag test was done second. Now, test the interrupt flag and use
      the unlikely macro.
      Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
      Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      0ede4a60
  3. 09 May, 2012 2 commits
    • Jacob E Keller's avatar
      ixgbe: Enable timesync clock-out feature for PPS support on X540 · 681ae1ad
      Jacob E Keller authored
      
      
      This patch enables the PPS system in the PHC framework, by enabling
      the clock-out feature on the X540 device. Causes the SDP0 to be set as
      a 1Hz clock. Also configures the timesync interrupt cause in order to
      report each pulse to the PPS via the PHC framework, which can be used
      for general system clock synchronization. (This allows a stable method
      for tuning the general system time via the on-board SYSTIM register
      based clock.)
      Signed-off-by: default avatarJacob E Keller <jacob.e.keller@intel.com>
      Tested-by: default avatarStephen Ko <stephen.s.ko@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      681ae1ad
    • Jacob Keller's avatar
      ixgbe: Hardware Timestamping + PTP Hardware Clock (PHC) · 3a6a4eda
      Jacob Keller authored
      
      
      This patch enables hardware timestamping for use with PTP software by
      extracting a ns counter from an arbitrary fixed point cycles counter.
      The hardware generates SYSTIME registers using the DMA tick which
      changes based on the current link speed. These SYSTIME registers are
      converted to ns using the cyclecounter and timecounter structures
      provided by the kernel. Using the SO_TIMESTAMPING api, software can
      enable and access timestamps for PTP packets.
      
      The SO_TIMESTAMPING API has space for 3 different kinds of timestamps,
      SYS, RAW, and SOF. SYS hardware timestamps are hardware ns values that
      are then scaled to the software clock. RAW hardware timestamps are the
      direct raw value of the ns counter. SOF software timestamps are the
      software timestamp calculated as close as possible to the software
      transmit, but are not offloaded to the hardware. This patch only
      supports the RAW hardware timestamps due to inefficiency of the SYS
      design.
      
      This patch also enables the PHC subsystem features for atomically
      adjusting the cycle register, and adjusting the clock frequency in
      parts per billion. This frequency adjustment works by slightly
      adjusting the value added to the cycle registers each DMA tick. This
      causes the hardware registers to overflow rapidly (approximately once
      every 34 seconds, when at 10gig link). To solve this, the timecounter
      structure is used, along with a timer set for every 25 seconds. This
      allows for detecting register overflow and converting the cycle
      counter registers into ns values needed for providing useful
      timestamps to the network stack.
      
      Only the basic required clock functions are supported at this time,
      although the hardware supports some ancillary features and these could
      easily be enabled in the future.
      
      Note that use of this hardware timestamping requires modifying daemon
      software to use the SO_TIMESTAMPING API for timestamps, and the
      ptp_clock PHC framework for accessing the clock. The timestamps have
      no relation to the system time at all, so software must use the posix
      clock generated by the PHC framework instead.
      Signed-off-by: default avatarJacob E Keller <jacob.e.keller@intel.com>
      Tested-by: default avatarStephen Ko <stephen.s.ko@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      3a6a4eda