1. 17 Jul, 2012 1 commit
  2. 21 Jun, 2012 3 commits
  3. 23 May, 2012 1 commit
  4. 17 May, 2012 1 commit
  5. 13 May, 2012 1 commit
  6. 09 May, 2012 5 commits
  7. 04 May, 2012 1 commit
  8. 03 May, 2012 3 commits
  9. 12 Apr, 2012 1 commit
  10. 21 Mar, 2012 3 commits
  11. 01 Feb, 2012 1 commit
  12. 25 Jan, 2012 1 commit
  13. 24 Jan, 2012 1 commit
  14. 06 Jan, 2012 1 commit
    • Jerome Glisse's avatar
      drm/radeon: GPU virtual memory support v22 · 721604a1
      Jerome Glisse authored
      Virtual address space are per drm client (opener of /dev/drm).
      Client are in charge of virtual address space, they need to
      map bo into it by calling DRM_RADEON_GEM_VA ioctl.
      First 16M of virtual address space is reserved by the kernel.
      Once using 2 level page table we should be able to have a small
      vram memory footprint for each pt (there would be one pt for all
      gart, one for all vram and then one first level for each virtual
      address space).
      Plan include using the sub allocator for a common vm page table
      area and using memcpy to copy vm page table in & out. Or use
      a gart object and copy things in & out using dma.
      v2: agd5f fixes:
      - Add vram base offset for vram pages.  The GPU physical address of a
      vram page is FB_OFFSET + page offset.  FB_OFFSET is 0 on discrete
      cards and the physical bus address of the stolen memory on
      integrated chips.
      - VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
      v3: agd5f:
      - integrate with the semaphore/multi-ring stuff
      - rebase on top ttm dma & multi-ring stuff
      - userspace is now in charge of the address space
      - no more specific cs vm ioctl, instead cs ioctl has a new
      - properly handle mem == NULL case from move_notify callback
      - fix the vm cleanup path
      - fix update of page table to only happen on valid mem placement
      - add tlb flush for each vm context
      - add flags to define mapping property (readable, writeable, snooped)
      - make ring id implicit from ib->fence->ring, up to each asic callback
        to then do ring specific scheduling if vm ib scheduling function
      - add query for ib limit and kernel reserved virtual space
      - rename vm->size to max_pfn (maximum number of page)
      - update gem_va ioctl to also allow unmap operation
      - bump kernel version to allow userspace to query for vm support
      - rebuild page table only when bind and incrementaly depending
        on bo referenced by cs and that have been moved
      - allow virtual address space to grow
      - use sa allocator for vram page table
      - return invalid when querying vm limit on non cayman GPU
      - dump vm fault register on lockup
      v10: agd5f:
      - Move the vm schedule_ib callback to a standalone function, remove
        the callback and use the existing ib_execute callback for VM IBs.
      - rebase on top of lastest Linus
      v12: agd5f:
      - remove spurious backslash
      - set IB vm_id to 0 in radeon_ib_get()
      v13: agd5f:
      - fix handling of RADEON_CHUNK_ID_FLAGS
      - fix va destruction
      - fix suspend resume
      - forbid bo to have several different va in same vm
      - rebase
      - cleanup left over of vm init/fini
      v17: agd5f:
      - cs checker
      v18: agd5f:
      - reworks the CS ioctl to better support multiple rings and
      VM.  Rather than adding a new chunk id for VM, just re-use the
      IB chunk id and add a new flags for VM mode.  Also define additional
      dwords for the flags chunk id to define the what ring we want to use
      (gfx, compute, uvd, etc.) and the priority.
      - fix cs fini in weird case of no ib
      - semi working flush fix for ni
      - rebase on top of sa allocator changes
      v20: agd5f:
      - further CS ioctl cleanups from Christian's comments
      v21: agd5f:
      - integrate CS checker improvements
      v22: agd5f:
      - final cleanups for release, only allow VM CS on cayman
      Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  15. 05 Jan, 2012 2 commits
  16. 20 Dec, 2011 6 commits
  17. 06 Dec, 2011 1 commit
  18. 11 Nov, 2011 1 commit
  19. 18 Oct, 2011 1 commit
  20. 10 Oct, 2011 2 commits
    • Alex Deucher's avatar
      drm/radeon/kms: set DMA mask properly on newer PCI asics · 005a83f1
      Alex Deucher authored
      If a card wasn't PCIE, we always set the DMA mask to 32 bits.
      This is only applies to the old rage128/r1xx gart block on
      early radeon asics (~r1xx-r4xx).  Newer PCI and IGP cards
      can handle 40 bits just fine.
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      Cc: Chen Jie <chenj@lemote.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
    • Michael Witten's avatar
      Michael Witten authored
      The value of RADEON_DEBUGFS_MAX_NUM_FILES has been used to
      specify the size of an array, each element of which looks
      like this:
        struct radeon_debugfs {
                struct drm_info_list    *files;
                unsigned                num_files;
      Consequently, the number of debugfs files may be much greater
      than RADEON_DEBUGFS_MAX_NUM_FILES, something that the current
      code ignores:
        if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
                DRM_ERROR("Reached maximum number of debugfs files.\n");
                DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
                return -EINVAL;
      This commit fixes this make, and accordingly renames:
      Signed-off-by: default avatarMichael Witten <mfwitten@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  21. 22 Aug, 2011 1 commit
  22. 12 Aug, 2011 1 commit
  23. 04 Aug, 2011 1 commit