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  1. 31 May, 2016 1 commit
  2. 11 May, 2016 1 commit
    • Julien Grall's avatar
      arm64: cpuinfo: Missing NULL terminator in compat_hwcap_str · f228b494
      Julien Grall authored
      The loop that browses the array compat_hwcap_str will stop when a NULL
      is encountered, however NULL is missing at the end of array. This will
      lead to overrun until a NULL is found somewhere in the following memory.
      In reality, this works out because the compat_hwcap2_str array tends to
      follow immediately in memory, and that *is* terminated correctly.
      Furthermore, the unsigned int compat_elf_hwcap is checked before
      printing each capability, so we end up doing the right thing because
      the size of the two arrays is less than 32. Still, this is an obvious
      mistake and should be fixed.
      
      Note for backporting: commit 12d11817 ("arm64: Move
      /proc/cpuinfo handling code") moved this code in v4.4. Prior to that
      commit, the same change should be made in arch/arm64/kernel/setup.c.
      
      Fixes: 44b82b77 "arm64: Fix up /proc/cpuinfo"
      Cc: <stable@vger.kernel.org> # v3.19+ (but see note above prior to v4.4)
      Signed-off-by: default avatarJulien Grall <julien.grall@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      f228b494
  3. 20 Apr, 2016 1 commit
  4. 04 Mar, 2016 1 commit
    • Mark Rutland's avatar
      arm64: make mrs_s prefixing implicit in read_cpuid · 1cc6ed90
      Mark Rutland authored
      Commit 0f54b14e ("arm64: cpufeature: Change read_cpuid() to use
      sysreg's mrs_s macro") changed read_cpuid to require a SYS_ prefix on
      register names, to allow manual assembly of registers unknown by the
      toolchain, using tables in sysreg.h.
      
      This interacts poorly with commit 42b55734 ("efi/arm64: Check
      for h/w support before booting a >4 KB granular kernel"), which is
      curretly queued via the tip tree, and uses read_cpuid without a SYS_
      prefix. Due to this, a build of next-20160304 fails if EFI and 64K pages
      are selected.
      
      To avoid this issue when trees are merged, move the required SYS_
      prefixing into read_cpuid, and revert all of the updated callsites to
      pass plain register names. This effectively reverts the bulk of commit
      0f54b14e.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: James Morse <james.morse@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      1cc6ed90
  5. 26 Feb, 2016 1 commit
  6. 18 Feb, 2016 2 commits
  7. 19 Nov, 2015 1 commit
  8. 21 Oct, 2015 6 commits
    • Dave Martin's avatar
      arm64: Constify hwcap name string arrays · 9299b247
      Dave Martin authored
      The hwcap string arrays used for generating the contents of
      /proc/cpuinfo are currently arrays of non-const pointers.
      
      There's no need for these pointers to be mutable, so this patch makes
      them const so that they can be moved to .rodata.
      Signed-off-by: default avatarDave Martin <Dave.Martin@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      9299b247
    • Suzuki K. Poulose's avatar
      arm64: Delay cpu feature capability checks · dbb4e152
      Suzuki K. Poulose authored
      At the moment we run through the arm64_features capability list for
      each CPU and set the capability if one of the CPU supports it. This
      could be problematic in a heterogeneous system with differing capabilities.
      Delay the CPU feature checks until all the enabled CPUs are up(i.e,
      smp_cpus_done(), so that we can make better decisions based on the
      overall system capability. Once we decide and advertise the capabilities
      the alternatives can be applied. From this state, we cannot roll back
      a feature to disabled based on the values from a new hotplugged CPU,
      due to the runtime patching and other reasons. So, for all new CPUs,
      we need to make sure that they have the established system capabilities.
      Failing which, we bring the CPU down, preventing it from turning online.
      Once the capabilities are decided, any new CPU booting up goes through
      verification to ensure that it has all the enabled capabilities and also
      invokes the respective enable() method on the CPU.
      
      The CPU errata checks are not delayed and is still executed per-CPU
      to detect the respective capabilities. If we ever come across a non-errata
      capability that needs to be checked on each-CPU, we could introduce them via
      a new capability table(or introduce a flag), which can be processed per CPU.
      
      The next patch will make the feature checks use the system wide
      safe value of a feature register.
      
      NOTE: The enable() methods associated with the capability is scheduled
      on all the CPUs (which is the only use case at the moment). If we need
      a different type of 'enable()' which only needs to be run once on any CPU,
      we should be able to handle that when needed.
      Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: default avatarDave Martin <Dave.Martin@arm.com>
      [catalin.marinas@arm.com: static variable and coding style fixes]
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      dbb4e152
    • Suzuki K. Poulose's avatar
      arm64: Consolidate CPU Sanity check to CPU Feature infrastructure · 3086d391
      Suzuki K. Poulose authored
      This patch consolidates the CPU Sanity check to the new infrastructure.
      
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: default avatarDave Martin <Dave.Martin@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      3086d391
    • Suzuki K. Poulose's avatar
      arm64: Keep track of CPU feature registers · 3c739b57
      Suzuki K. Poulose authored
      This patch adds an infrastructure to keep track of the CPU feature
      registers on the system. For each register, the infrastructure keeps
      track of the system wide safe value of the feature bits. Also, tracks
      the which fields of a register should be matched strictly across all
      the CPUs on the system for the SANITY check infrastructure.
      
      The feature bits are classified into following 3 types depending on
      the implication of the possible values. This information is used to
      decide the safe value for a feature.
      
      LOWER_SAFE  - The smaller value is safer
      HIGHER_SAFE - The bigger value is safer
      EXACT       - We can't decide between the two, so a predefined safe_value is used.
      
      This infrastructure will be later used to make better decisions for:
      
       - Kernel features (e.g, KVM, Debug)
       - SANITY Check
       - CPU capability
       - ELF HWCAP
       - Exposing CPU Feature register to userspace.
      Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: default avatarDave Martin <Dave.Martin@arm.com>
      [catalin.marinas@arm.com: whitespace fix]
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      3c739b57
    • Suzuki K. Poulose's avatar
      arm64: Move /proc/cpuinfo handling code · 12d11817
      Suzuki K. Poulose authored
      This patch moves the /proc/cpuinfo handling code:
      
      arch/arm64/kernel/{setup.c to cpuinfo.c}
      
      No functional changes
      Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: default avatarDave Martin <Dave.Martin@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      12d11817
    • Suzuki K. Poulose's avatar
      arm64: Move mixed endian support detection · cdcf817b
      Suzuki K. Poulose authored
      Move the mixed endian support detection code to cpufeature.c
      from cpuinfo.c. This also moves the update_cpu_features()
      used by mixed endian detection code, which will get more
      functionality.
      
      Also moves the ID register field shifts to asm/sysreg.h,
      where all the useful definitions will end up in later patches.
      Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
      Tested-by: default avatarDave Martin <Dave.Martin@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      cdcf817b
  9. 30 Mar, 2015 1 commit
  10. 23 Jan, 2015 1 commit
  11. 15 Jan, 2015 1 commit
  12. 07 Jan, 2015 1 commit
  13. 25 Nov, 2014 4 commits
    • Mark Rutland's avatar
      arm64: sanity checks: add ID_AA64DFR{0,1}_EL1 · 3eebdbe5
      Mark Rutland authored
      While we currently expect self-hosted debug support to be identical
      across CPUs, we don't currently sanity check this.
      
      This patch adds logging of the ID_AA64DFR{0,1}_EL1 values and associated
      sanity checking code.
      
      It's not clear to me whether we need to check PMUVer, TraceVer, and
      DebugVer, as we don't currently rely on these fields at all.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      3eebdbe5
    • Mark Rutland's avatar
      arm64: sanity checks: add missing newline to print · efdf4211
      Mark Rutland authored
      A missing newline in the WARN_TAINT_ONCE string results in ugly and
      somewhat difficult to read output in the case of a sanity check failure,
      as the next print does not appear on a new line:
      
        Unsupported CPU feature variation.Modules linked in:
      
      This patch adds the missing newline, fixing the output formatting.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      efdf4211
    • Mark Rutland's avatar
      arm64: sanity checks: ignore ID_MMFR0.AuxReg · 9760270c
      Mark Rutland authored
      It seems that Cortex-A53 r0p4 added support for AIFSR and ADFSR, and
      ID_MMFR0.AuxReg has been updated accordingly to report this fact. As
      Cortex-A53 could be paired with CPUs which do not implement these
      registers (e.g. all current revisions of Cortex-A57), this may trigger a
      sanity check failure at boot.
      
      The AuxReg value describes the availability of the ACTLR, AIFSR, and
      ADFSR registers, which are only of use to 32-bit guest OSs, and have
      IMPLEMENTATION DEFINED contents. Given the nature of these registers it
      is likely that KVM will need to trap accesses regardless of whether the
      CPUs are heterogeneous.
      
      This patch masks out the ID_MMFR0.AuxReg value from the sanity checks,
      preventing spurious warnings at boot time.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reported-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9760270c
    • Andre Przywara's avatar
      arm64: detect silicon revisions and set cap bits accordingly · e116a375
      Andre Przywara authored
      After each CPU has been started, we iterate through a list of
      CPU features or bugs to detect CPUs which need (or could benefit
      from) kernel code patches.
      For each feature/bug there is a function which checks if that
      particular CPU is affected. We will later provide some more generic
      functions for common things like testing for certain MIDR ranges.
      We do this for every CPU to cover big.LITTLE systems properly as
      well.
      If a certain feature/bug has been detected, the capability bit will
      be set, so that later the call to apply_alternatives() will trigger
      the actual code patching.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      e116a375
  14. 08 Sep, 2014 2 commits
  15. 18 Aug, 2014 1 commit
  16. 01 Aug, 2014 1 commit
    • Mark Rutland's avatar
      arm64: add newline to I-cache policy string · ea171967
      Mark Rutland authored
      Due to a missing newline in the I-cache policy detection log output,
      it's possible to get some ratehr unfortunate output at boot time:
      
      CPU1: Booted secondary processor
      Detected VIPT I-cache on CPU1CPU2: Booted secondary processor
      Detected VIPT I-cache on CPU2CPU3: Booted secondary processor
      Detected VIPT I-cache on CPU3CPU4: Booted secondary processor
      Detected PIPT I-cache on CPU4CPU5: Booted secondary processor
      Detected PIPT I-cache on CPU5Brought up 6 CPUs
      SMP: Total of 6 processors activated.
      
      This patch adds the missing newline to the format string, cleaning up
      the output.
      
      Fixes: 59ccc0d4 ("arm64: cachetype: report weakest cache policy")
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      ea171967
  17. 18 Jul, 2014 3 commits
    • Mark Rutland's avatar
      arm64: add runtime system sanity checks · 127161aa
      Mark Rutland authored
      Unexpected variation in certain system register values across CPUs is an
      indicator of potential problems with a system. The kernel expects CPUs
      to be mostly identical in terms of supported features, even in systems
      with heterogeneous CPUs, with uniform instruction set support being
      critical for the correct operation of userspace.
      
      To help detect issues early where hardware violates the expectations of
      the kernel, this patch adds simple runtime sanity checks on important ID
      registers in the bring up path of each CPU.
      
      Where CPUs are fundamentally mismatched, set TAINT_CPU_OUT_OF_SPEC.
      Given that the kernel assumes CPUs are identical feature wise, let's not
      pretend that we expect such configurations to work. Supporting such
      configurations would require massive rework, and hopefully they will
      never exist.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      127161aa
    • Mark Rutland's avatar
      arm64: cachetype: report weakest cache policy · 59ccc0d4
      Mark Rutland authored
      In big.LITTLE systems, the I-cache policy may differ across CPUs, and
      thus we must always meet the most stringent maintenance requirements of
      any I-cache in the system when performing maintenance to ensure
      correctness. Unfortunately this requirement is not met as we always look
      at the current CPU's cache type register to determine the maintenance
      requirements.
      
      This patch causes the I-cache policy of all CPUs to be taken into
      account for icache_is_aliasing and icache_is_aivivt. If any I-cache in
      the system is aliasing or AIVIVT, the respective function will return
      true. At boot each CPU may set flags to identify that at least one
      I-cache in the system is aliasing and/or AIVIVT.
      
      The now unused and potentially misleading icache_policy function is
      removed.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      59ccc0d4
    • Mark Rutland's avatar
      arm64: cpuinfo: record cpu system register values · df857416
      Mark Rutland authored
      Several kernel subsystems need to know details about CPU system register
      values, sometimes for CPUs other than that they are executing on. Rather
      than hard-coding system register accesses and cross-calls for these
      cases, this patch adds logic to record various system register values at
      boot-time. This may be used for feature reporting, firmware bug
      detection, etc.
      
      Separate hooks are added for the boot and hotplug paths to enable
      one-time intialisation and cold/warm boot value mismatch detection in
      later patches.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      df857416