- 28 Apr, 2012 1 commit
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Alex Deucher authored
Makes Nutmeg DP to VGA bridges work for me. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=42490 Noticed by Jerome Glisse (after weeks of debugging). Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 27 Apr, 2012 1 commit
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Alex Deucher authored
Seems to be more stable on certain monitors. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48880 Signed-off-by:
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- 26 Mar, 2012 1 commit
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Alex Deucher authored
Using the bpc (bits per color) specified by the monitor can cause problems in some cases. Until we get a better handle on how to deal with those cases, just use a bpc of 8. Reported-by:
Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by:
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- 21 Mar, 2012 7 commits
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Alex Deucher authored
It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by:
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Alex Deucher authored
Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Alex Deucher authored
On TN, UNIPHYA always uses PPLL2, UNIPHYB/C/D/E/F can use either PPLL1 or PPLL0. Signed-off-by:
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Alex Deucher authored
DCE6.1 uses EXT_PLL1 for disp eng. Signed-off-by:
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Alex Deucher authored
Rename the function to better match the functionality. DCPLL became PLL0 on DCE6. Signed-off-by:
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Alex Deucher authored
Each pair of crtcs (0/1, 2/3, 4/5) can be power gated. Make sure the power is applied when the crtc is in use and only power down the pair when both are off. Signed-off-by:
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Alex Deucher authored
The hw no longer has the bits and the table is removed. Signed-off-by:
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- 13 Feb, 2012 1 commit
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Jerome Glisse authored
evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by:Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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- 01 Feb, 2012 1 commit
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Michel Dänzer authored
The value of this register is transferred to the V_COUNTER register at the beginning of vertical blank. V_COUNTER is the reference for VLINE waits and goes from VIEWPORT_Y_START to VIEWPORT_Y_START+VIEWPORT_HEIGHT during scanout, so if VIEWPORT_Y_START is not 0, V_COUNTER actually went backwards at the beginning of vertical blank, and VLINE waits excluding the whole scanout area could never finish (possibly only if VIEWPORT_Y_START is larger than the length of vertical blank in scanlines). Setting DESKTOP_HEIGHT to the framebuffer height should prevent this for any kind of VLINE wait. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=45329 . CC: stable@vger.kernel.org Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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- 24 Jan, 2012 2 commits
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Alex Deucher authored
HDMI 1.3 defines single link clocks up to 340 Mhz. Refine the current dual link checks to only enable dual link for DVI > 165 Mhz or HDMI > 340 Mhz if the hw supports HDMI 1.3 (DCE3+). Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=44755 Signed-off-by:
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Alex Deucher authored
We really only need to set it up once on init or resume rather than on every mode set. Signed-off-by:
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- 20 Dec, 2011 2 commits
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Dave Airlie authored
If the bpc is set from the connector is 0, we then use it later to adjust in a special case the HDMI pixel clock, however if the bpc is 0, we end up passing a 0 pixel clock into the code. I'm not sure if this is the correct answer or if we should avoid the HDMI clock adjustment for 0 values. This fixes a divide by 0 on my Llano system with a HDMI monitor and hdmi audio enabled. Reviewed-by:
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Ville Syrjälä authored
Otherwise each driver would need to keep the information inside their own framebuffer object structure. Also add offsets[]. BOs on the other hand are driver specific, so those can be kept in driver specific structures. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 02 Dec, 2011 1 commit
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Alex Deucher authored
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43191 Signed-off-by:
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- 11 Nov, 2011 1 commit
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Alex Deucher authored
It's already called via the DPMS functions. Signed-off-by:
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- 01 Nov, 2011 3 commits
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Alex Deucher authored
DP MST is DP multi-stream support, part of DP 1.2. v2: switch to a helper macro as suggested by Michel. Signed-off-by:
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Alex Deucher authored
Return the encoder id rather than a boolean. This is needed for differentiate between multiple DP bridge chips. Signed-off-by:
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Alex Deucher authored
The logic was messy and hard to follow. Signed-off-by:
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- 18 Oct, 2011 1 commit
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Alex Deucher authored
It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by:
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- 25 Jul, 2011 1 commit
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Benjamin Herrenschmidt authored
v6 of the structure was programmed incorrectly: args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); ulPixelClock is a 24-bit bitfield. This statement would thus do a 32-bit swap of (clock / 10) and drop the top 8 bits which are ... the LSB. Not what we want. Instead use masks & shifts. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by:
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- 16 Jun, 2011 1 commit
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Alex Deucher authored
Need to set the external transmitter type properly in AdjustPixelClock to get the properly output. Signed-off-by:
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- 01 Jun, 2011 1 commit
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Alex Deucher authored
Otherwise, no vblank interrupts. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=37522 Signed-off-by:
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- 23 May, 2011 1 commit
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Alex Deucher authored
Signed-off-by:
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- 22 May, 2011 2 commits
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Alex Deucher authored
For DP/eDP, always use the standard DP SS indices. Signed-off-by:
Dave Airlie <airlied@gmail.com>
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Alex Deucher authored
If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by:
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- 20 May, 2011 4 commits
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Alex Deucher authored
Fusion hardware often has DP to VGA/LVDS/TMDS bridges to handle non-DP encoders. Internally we treat them mostly like DP. Signed-off-by:
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Alex Deucher authored
In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, depending on the asic. The crtc virtual pixel clock is derived from the DP ref clock. - DCE4: PPLL or ext clock - DCE5: DCPLL or ext clock Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip PPLL/DCPLL programming and only program the DP DTO for the crtc virtual pixel clock. Signed-off-by:
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Alex Deucher authored
- properly mask the ss type - don't enable ss if type is external or percentage is 0 - if ss enabled and type is external, set ref_div_src to ext clock - prefer ASIC_INTERNAL_SS_ON_DP to LCD_Info SS_Id for eDP - fix ss amount calculation Signed-off-by:
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Alex Deucher authored
Signed-off-by:
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- 19 Apr, 2011 1 commit
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Alex Deucher authored
Prefer min m to max p only on pre-r7xx asics. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=36197 Signed-off-by:
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- 09 Apr, 2011 1 commit
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Alex Deucher authored
Prefer minm over maxp. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=35994 Signed-off-by:
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- 03 Apr, 2011 1 commit
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Alex Deucher authored
Avoid touching the flip setup regs while acceleration is running. Set them at modeset rather than during pageflip. Touching these regs while acceleration is active caused hangs on pre-avivo chips. These chips do not seem to be affected, but better safe than sorry, plus it avoids repeatedly reprogramming the regs every flip. Signed-off-by:
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- 22 Mar, 2011 1 commit
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Alex Deucher authored
ntsc seems to work fine with either algo, some pal TVs seem pickier. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=30832 Signed-off-by:
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- 15 Mar, 2011 1 commit
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Alex Deucher authored
Typo in the aspect scale setup. Signed-off-by:
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- 22 Feb, 2011 1 commit
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Daniel Vetter authored
... and switch it to container_of upcasting. v2: converted new pageflip code-paths. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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- 16 Feb, 2011 1 commit
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Alex Deucher authored
The fixed ref/post dividers are set by the AdjustPll table rather than the ss info table on dce4+. Make sure we enable the fractional feedback dividers when using a fixed post or ref divider on them as well. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=29272 Signed-off-by:
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- 14 Feb, 2011 1 commit
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Alex Deucher authored
The problematic boards have a recommended reference divider to be used when spread spectrum is enabled on the laptop panel. Enable the use of the recommended reference divider along with the new pll algo. v2: testing options v3: When using the fixed reference divider with LVDS, prefer min m to max p and use fractional feedback dividers. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28852 https://bugzilla.kernel.org/show_bug.cgi?id=24462 https://bugzilla.kernel.org/show_bug.cgi?id=26552 MacbookPro issues reported by Justin Mattock <justinmattock@gmail.com> Signed-off-by:
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