1. 03 Mar, 2007 1 commit
  2. 26 Feb, 2007 1 commit
  3. 17 Feb, 2007 2 commits
  4. 16 Feb, 2007 2 commits
  5. 14 Feb, 2007 1 commit
  6. 11 Feb, 2007 3 commits
    • Al Viro's avatar
      [PATCH] sort the devres mess out · 5ea81769
      Al Viro authored
      * Split the implementation-agnostic stuff in separate files.
      * Make sure that targets using non-default request_irq() pull
      * Introduce new symbols (HAS_IOPORT and HAS_IOMEM) defaulting to positive;
        allow architectures to turn them off (we needed these symbols anyway for
        dependencies of quite a few drivers).
      * protect the ioport-related parts of lib/devres.o with CONFIG_HAS_IOPORT.
      Signed-off-by: default avatarAl Viro <viro@zeniv.linux.org.uk>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
    • Christoph Lameter's avatar
      [PATCH] Set CONFIG_ZONE_DMA for arches with GENERIC_ISA_DMA · 5ac6da66
      Christoph Lameter authored
      As Andi pointed out: CONFIG_GENERIC_ISA_DMA only disables the ISA DMA
      channel management.  Other functionality may still expect GFP_DMA to
      provide memory below 16M.  So we need to make sure that CONFIG_ZONE_DMA is
      set independent of CONFIG_GENERIC_ISA_DMA.  Undo the modifications to
      mm/Kconfig where we made ZONE_DMA dependent on GENERIC_ISA_DMA and set
      theses explicitly in each arches Kconfig.
      Reviews must occur for each arch in order to determine if ZONE_DMA can be
      switched off.  It can only be switched off if we know that all devices
      supported by a platform are capable of performing DMA transfers to all of
      memory (Some arches already support this: uml, avr32, sh sh64, parisc and
      In order to switch ZONE_DMA off conditionally, one would have to establish
      a scheme by which one can assure that no drivers are enabled that are only
      capable of doing I/O to a part of memory, or one needs to provide an
      alternate means of performing an allocation from a specific range of memory
      (like provided by alloc_pages_range()) and insure that all drivers use that
      call.  In that case the arches alloc_dma_coherent() may need to be modified
      to call alloc_pages_range() instead of relying on GFP_DMA.
      Signed-off-by: default avatarChristoph Lameter <clameter@sgi.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
    • Ben Dooks's avatar
      [ARM] 4157/2: S3C24XX: move arch/arch/mach-s3c2410 into cpu components · a21765a7
      Ben Dooks authored
      The following patch and script moves the arch/arm/mach-s3c2410
      directory into arch/arm/plat-s3c24xx for the generic core code
      and inti arch/arm/mach-s3c{cpu} for the cpu/machine support files
      Include directory include/asm-arm/plat-s3c24xx is added for the
      core include files.
      Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  7. 09 Feb, 2007 1 commit
  8. 08 Feb, 2007 2 commits
  9. 13 Dec, 2006 2 commits
  10. 08 Dec, 2006 1 commit
    • David Howells's avatar
      [PATCH] LOG2: Implement a general integer log2 facility in the kernel · f0d1b0b3
      David Howells authored
      This facility provides three entry points:
      	ilog2()		Log base 2 of unsigned long
      	ilog2_u32()	Log base 2 of u32
      	ilog2_u64()	Log base 2 of u64
      These facilities can either be used inside functions on dynamic data:
      	int do_something(long q)
      		y = ilog2(x)
      Or can be used to statically initialise global variables with constant values:
      	unsigned n = ilog2(27);
      When performing static initialisation, the compiler will report "error:
      initializer element is not constant" if asked to take a log of zero or of
      something not reducible to a constant.  They treat negative numbers as
      When not dealing with a constant, they fall back to using fls() which permits
      them to use arch-specific log calculation instructions - such as BSR on
      x86/x86_64 or SCAN on FRV - if available.
      [akpm@osdl.org: MMC fix]
      Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Herbert Xu <herbert@gondor.apana.org.au>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Wojtek Kaniewski <wojtekka@toxygen.net>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
  11. 07 Dec, 2006 1 commit
    • Dan Williams's avatar
      [ARM] 3995/1: iop13xx: add iop13xx support · 285f5fa7
      Dan Williams authored
      The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
      Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
      controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
      PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
      a system-on-a-chip RAID subsystem engine.
      The iop342 processor replaces the SAS controller with a second Xscale core
      for dual core embedded applications.
      The iop341 processor is the single core version of iop342.
      This patch supports the two Intel customer reference platforms iq81340mc
      for external storage and iq81340sc for direct attach (HBA) development.
      The developer's manual is available here:
      * removed virtual addresses from resource definitions
      * cleaned up some unnecessary #include's
      Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  12. 03 Dec, 2006 1 commit
    • Lennert Buytenhek's avatar
      [ARM] 3881/4: xscale: clean up cp0/cp1 handling · afe4b25e
      Lennert Buytenhek authored
      XScale cores either have a DSP coprocessor (which contains a single
      40 bit accumulator register), or an iWMMXt coprocessor (which contains
      eight 64 bit registers.)
      Because of the small amount of state in the DSP coprocessor, access to
      the DSP coprocessor (CP0) is always enabled, and DSP context switching
      is done unconditionally on every task switch.  Access to the iWMMXt
      coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
      first issued, and iWMMXt context switching is done lazily.
      CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
      have iWMMXt support', but boards are supposed to select this config
      symbol by hand, and at least one pxa27x board doesn't get this right,
      so on that board, proc-xscale.S will incorrectly assume that we have a
      DSP coprocessor, enable CP0 on boot, and we will then only save the
      first iWMMXt register (wR0) on context switches, which is Bad.
      This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
      might have iWMMXt support, and we will enable iWMMXt context switching
      if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
      kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
      state over context switches, and running a CONFIG_IWMMXT=y kernel on a
      non-iWMMXt capable CPU will still do DSP context save/restore.
      These changes should make iWMMXt work on PXA3xx, and as a side effect,
      enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
      as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
      as well as setting and using HWCAP_IWMMXT properly.
      Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
      Acked-by: default avatarDan Williams <dan.j.williams@intel.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  13. 01 Dec, 2006 1 commit
  14. 20 Nov, 2006 1 commit
  15. 03 Oct, 2006 1 commit
  16. 28 Sep, 2006 3 commits
  17. 27 Sep, 2006 1 commit
    • Hyok S. Choi's avatar
      [ARM] nommu: manage the CP15 things · f12d0d7c
      Hyok S. Choi authored
      All the current CP15 access codes in ARM arch can be categorized and
      conditioned by the defines as follows:
           Related operation	Safe condition
        a. any CP15 access	!CPU_CP15
        b. alignment trap	CPU_CP15_MMU
        c. D-cache(C-bit)	CPU_CP15
        d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
      				CPU_ARM720 || CPU_ARM740 ||
      				CPU_XSCALE || CPU_XSC3 )
        e. alternate vector	CPU_CP15 && !CPU_ARM740
        f. TTB		CPU_CP15_MMU
        g. Domain		CPU_CP15_MMU
        h. FSR/FAR		CPU_CP15_MMU
      For example, alternate vector is supported if and only if
      "CPU_CP15 && !CPU_ARM740" is satisfied.
      Signed-off-by: default avatarHyok S. Choi <hyok.choi@samsung.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  18. 25 Sep, 2006 3 commits
  19. 20 Sep, 2006 1 commit
  20. 01 Jul, 2006 1 commit
    • Thomas Gleixner's avatar
      [ARM] 3692/1: ARM: coswitch irq handling to the generic implementation · 4a2581a0
      Thomas Gleixner authored
      Patch from Thomas Gleixner
      From: Thomas Gleixner <tglx@linutronix.de>
      Switch the ARM irq core handling to the generic implementation. The
      ARM specific header files now contain mostly migration stubs and
      helper macros. Note that each machine type must be converted after
      this step seperately. This was seperated out from the patch for easier
      The main changes for the machine type code is the conversion of the
      type handlers to a 'type flow' and 'chip' model. This affects only the
      multiplex interrupt handlers. A conversion macro needs to be added to
      those implementations, which defines the data structure which is
      registered by the set_irq_chained_handler() macro.
      Some minor fixups of include files and the conversion of data
      structure access is necessary all over the place.
      The mostly macro based conversion was provided to allow an easy
      migration of the existing implementations.
      The code compiles on all defconfigs available in arch/arm/configs
      except those which were broken also before applying the conversion
      The code has been boot and runtime tested on most ARM platforms. The
      results of an extensive testing and bugfixing series can be found
      at: http://www.linutronix.de/index.php?page=testing
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  21. 29 Jun, 2006 2 commits
  22. 28 Jun, 2006 2 commits
  23. 26 Jun, 2006 2 commits
  24. 25 Jun, 2006 1 commit
  25. 20 Jun, 2006 1 commit
  26. 19 Jun, 2006 1 commit
  27. 18 Jun, 2006 1 commit