1. 31 Aug, 2011 3 commits
  2. 01 Jul, 2011 2 commits
    • Peter Zijlstra's avatar
      perf, arch: Add generic NODE cache events · 89d6c0b5
      Peter Zijlstra authored
      
      
      Add a NODE level to the generic cache events which is used to measure
      local vs remote memory accesses. Like all other cache events, an
      ACCESS is HIT+MISS, if there is no way to distinguish between reads
      and writes do reads only etc..
      
      The below needs filling out for !x86 (which I filled out with
      unsupported events).
      
      I'm fairly sure ARM can leave it like that since it doesn't strike me as
      an architecture that even has NUMA support. SH might have something since
      it does appear to have some NUMA bits.
      
      Sparc64, PowerPC and MIPS certainly want a good look there since they
      clearly are NUMA capable.
      Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: David Miller <davem@davemloft.net>
      Cc: Anton Blanchard <anton@samba.org>
      Cc: David Daney <ddaney@caviumnetworks.com>
      Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Robert Richter <robert.richter@amd.com>
      Cc: Stephane Eranian <eranian@google.com>
      Link: http://lkml.kernel.org/r/1303508226.4865.8.camel@laptop
      
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      89d6c0b5
    • Peter Zijlstra's avatar
      perf: Remove the nmi parameter from the swevent and overflow interface · a8b0ca17
      Peter Zijlstra authored
      
      
      The nmi parameter indicated if we could do wakeups from the current
      context, if not, we would set some state and self-IPI and let the
      resulting interrupt do the wakeup.
      
      For the various event classes:
      
        - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from
          the PMI-tail (ARM etc.)
        - tracepoint: nmi=0; since tracepoint could be from NMI context.
        - software: nmi=[0,1]; some, like the schedule thing cannot
          perform wakeups, and hence need 0.
      
      As one can see, there is very little nmi=1 usage, and the down-side of
      not using it is that on some platforms some software events can have a
      jiffy delay in wakeup (when arch_irq_work_raise isn't implemented).
      
      The up-side however is that we can remove the nmi parameter and save a
      bunch of conditionals in fast paths.
      Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Michael Cree <mcree@orcon.net.nz>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
      Cc: Anton Blanchard <anton@samba.org>
      Cc: Eric B Munson <emunson@mgebm.net>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: David S. Miller <davem@davemloft.net>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Jason Wessel <jason.wessel@windriver.com>
      Cc: Don Zickus <dzickus@redhat.com>
      Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org
      
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      a8b0ca17
  3. 26 Mar, 2011 1 commit
  4. 02 Feb, 2011 1 commit
  5. 04 Dec, 2010 2 commits
    • Will Deacon's avatar
      ARM: 6521/1: perf: use raw_spinlock_t for pmu_lock · 961ec6da
      Will Deacon authored
      
      
      For kernels built with PREEMPT_RT, critical sections protected
      by standard spinlocks are preemptible. This is not acceptable
      on perf as (a) we may be scheduled onto a different CPU whilst
      reading/writing banked PMU registers and (b) the latency when
      reading the PMU registers becomes unpredictable.
      
      This patch upgrades the pmu_lock spinlock to a raw_spinlock
      instead.
      Reported-by: default avatarJamie Iles <jamie@jamieiles.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      961ec6da
    • Will Deacon's avatar
      ARM: 6512/1: perf: fix warnings generated by sparse · 4d6b7a77
      Will Deacon authored
      
      
      Russell reported a number of warnings coming from sparse when
      checking the ARM perf_event.c files:
      
      | perf_event.c seems to also have problems too:
      |
      |   CHECK   arch/arm/kernel/perf_event.c
      |   arch/arm/kernel/perf_event.c:37:1: warning: symbol 'pmu_lock' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:70:1: warning: symbol 'cpu_hw_events' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:1006:1: warning: symbol 'armv6pmu_enable_event' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:1113:1: warning: symbol 'armv6pmu_stop' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:1956:6: warning: symbol 'armv7pmu_enable_event' was not declared. Should it be static?
      |   arch/arm/kernel/perf_event.c:3072:14: warning: incorrect type in argument 1 (different address spaces)
      |   arch/arm/kernel/perf_event.c:3072:14:    expected void const volatile [noderef] <asn:1>*<noident>
      |   arch/arm/kernel/perf_event.c:3072:14:    got struct frame_tail *tail
      |   arch/arm/kernel/perf_event.c:3074:49: warning: incorrect type in argument 2 (different address spaces)
      |   arch/arm/kernel/perf_event.c:3074:49:    expected void const [noderef] <asn:1>*from
      |   arch/arm/kernel/perf_event.c:3074:49:    got struct frame_tail *tail
      
      This patch resolves these issues so we can live in silence
      again.
      Reported-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      4d6b7a77
  6. 25 Nov, 2010 1 commit
    • Will Deacon's avatar
      ARM: perf: separate PMU backends into multiple files · 43eab878
      Will Deacon authored
      
      
      The ARM perf_event.c file contains all PMU backends and, as new PMUs
      are introduced, will continue to grow.
      
      This patch follows the example of x86 and splits the PMU implementations
      into separate files which are then #included back into the main
      file. Compile-time guards are added to each PMU file to avoid compiling
      in code that is not relevant for the version of the architecture which
      we are targetting.
      Acked-by: default avatarJean Pihet <j-pihet@ti.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      43eab878