1. 06 Mar, 2012 3 commits
  2. 28 Nov, 2011 1 commit
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  6. 27 Sep, 2011 1 commit
    • Paul Bolle's avatar
      doc: fix broken references · 395cf969
      Paul Bolle authored
      There are numerous broken references to Documentation files (in other
      Documentation files, in comments, etc.). These broken references are
      caused by typo's in the references, and by renames or removals of the
      Documentation files. Some broken references are simply odd.
      Fix these broken references, sometimes by dropping the irrelevant text
      they were part of.
      Signed-off-by: default avatarPaul Bolle <pebolle@tiscali.nl>
      Signed-off-by: default avatarJiri Kosina <jkosina@suse.cz>
  7. 17 Aug, 2011 1 commit
  8. 31 Jan, 2011 1 commit
  9. 08 Dec, 2010 2 commits
  10. 01 Oct, 2010 1 commit
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  12. 15 Feb, 2010 1 commit
  13. 30 Nov, 2008 1 commit
  14. 01 Oct, 2008 1 commit
  15. 06 Sep, 2008 1 commit
    • Lennert Buytenhek's avatar
      [ARM] 5241/1: provide ioremap_wc() · 1ad77a87
      Lennert Buytenhek authored
      This patch provides an ARM implementation of ioremap_wc().
      We use different page table attributes depending on which CPU we
      are running on:
      - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
        possible mapping types (CB=00/01/10/11).  We can't use any of the
        cached memory types (CB=10/11), since that breaks coherency with
        peripheral devices.  Both CB=00 and CB=01 are suitable for _wc, and
        CB=01 (Uncached/Buffered) allows the hardware more freedom than
        CB=00, so we'll use that.
        (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
        but isn't allowed to merge them, but there is no other mapping type
        we can use that allows the hardware to delay and merge stores, so
        we'll go with CB=01.)
      - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
        difference that on these platforms, CB=01 actually _does_ allow
        merging stores.  (If you want noncoalescing bufferable behavior
        on Xscale v1/v2, you need to use XCB=101.)
      - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
        mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
        in ARMv6 parlance).
        The ARMv6 ARM explicitly says that any accesses to Normal memory can
        be merged, which makes Normal memory more suitable for _wc mappings
        than Device or Strongly Ordered memory, as the latter two mapping
        types are guaranteed to maintain transaction number, size and order.
        We use the Uncached variety of Normal mappings for the same reason
        that we can't use C=1 mappings on ARMv5.
        The xsc3 Architecture Specification documents TEXCB=00100 as being
        Uncacheable and allowing coalescing of writes, which is also just
        what we need.
      Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  16. 07 Aug, 2008 1 commit
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  20. 05 May, 2007 1 commit
    • Russell King's avatar
      [ARM] mm 10: allow memory type to be specified with ioremap · 3603ab2b
      Russell King authored
      __ioremap() took a set of page table flags (specifically the cacheable
      and bufferable bits) to control the mapping type.  However, with
      the advent of ARMv6, this is far too limited.
      Replace the page table flags with a memory type index, so that the
      desired attributes can be selected from the mem_type table.
      Finally, to prevent silent miscompilation due to the differing
      arguments, rename the __ioremap() and __ioremap_pfn() functions.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  21. 09 Feb, 2007 1 commit
  22. 30 Nov, 2006 1 commit
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  27. 24 Mar, 2006 1 commit
  28. 09 Jan, 2006 1 commit
    • Deepak Saxena's avatar
      [ARM] 3070/2: Add __ioremap_pfn() API · 9d4ae727
      Deepak Saxena authored
      Patch from Deepak Saxena
      In working on adding 36-bit addressed supersection support to ioremap(),
      I came to the conclusion that it would be far simpler to do so by just
      splitting __ioremap() into a main external interface and adding an
      __ioremap_pfn() function that takes a pfn + offset into the page that
      __ioremap() can call. This way existing callers of __ioremap() won't have
      to change their code and 36-bit systems will just call __ioremap_pfn()
      and we will not have to deal with unsigned long long variables.
      Note that __ioremap_pfn() should _NOT_ be called directly by drivers
      but is reserved for use by arch_ioremap() implementations that map
      32-bit resource regions into the real 36-bit address and then call
      this new function.
      Signed-off-by: default avatarDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
  29. 05 Dec, 2005 1 commit
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