1. 10 Aug, 2011 2 commits
    • Jeff Kirsher's avatar
      amd: Move AMD (Lance) chipset drivers · b955f6ca
      Jeff Kirsher authored
      Moves the drivers for the AMD chipsets into drivers/net/ethernet/amd/
      and the necessary Kconfig and Makfile changes.
      The au1000 (Alchemy) driver was also moved into the same directory
      even though it is not a "Lance" driver.
      CC: Peter Maydell <pmaydell@chiark.greenend.org.uk>
      CC: Roman Hodek <Roman.Hodek@informatik.uni-erlangen.de>
      CC: "Maciej W. Rozycki" <macro@linux-mips.org>
      CC: Donald Becker <becker@scyld.com>
      CC: Sam Creasey <sammy@users.qual.net>
      CC: Miguel de Icaza <miguel@nuclecu.unam.mx>
      CC: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
      CC: Don Fry <pcnet32@frontier.com>
      CC: Geert Uytterhoeven <geert@linux-m68k.org>
      CC: Russell King <linux@arm.linux.org.uk>
      CC: David Davies <davies@maniac.ultranet.com>
      CC: "M.Hipp" <hippm@informatik.uni-tuebingen.de>
      CC: Pete Popov <ppopov@embeddedalley.com>
      CC: David Hinds <dahinds@users.sourceforge.net>
      CC: "Roger C. Pao" <rpao@paonet.org>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
    • Jeff Kirsher's avatar
      3c*/acenic/typhoon: Move 3Com Ethernet drivers · ca7a8e85
      Jeff Kirsher authored
      Moves the 3Com drivers into drivers/net/ethernet/3com/ and the necessary
      Kconfig and Makefile changes.
      Did not move the following drivers becuase they use a non-3Com
      chipset: 3c503, 3c505, 3c507, 3c523 and 3c527
      CC: Steffen Klassert <klassert@mathematik.tu-chemnitz.de>
      CC: David Dillow <dave@thedillows.org>
      CC: Jes Sorensen <jes@trained-monkey.org>
      CC: Alan Cox <alan@linux.intel.com>
      CC: David Hinds <dahinds@users.sourceforge.net>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      Acked-by: default avatarDavid Dillow <dave@thedillows.org>
  2. 03 Aug, 2011 1 commit
    • Len Brown's avatar
      mrst_pmu: driver for Intel Moorestown Power Management Unit · 6dccf9c5
      Len Brown authored
      The Moorestown (MRST) Power Management Unit (PMU) driver
      directs the SOC power states in the "Langwell" south complex (SCU).
      It hooks pci_platform_pm_ops[] and thus observes all PCI ".set_state"
      requests.  For devices in the SC, the pmu driver translates those
      PCI requests into the appropriate commands for the SCU.
      The PMU driver helps implement S0i3, a deep system idle power idle state.
      Entry into S0i3 is via cpuidle, just like regular processor c-states.
      S0i3 depends on pre-conditions including uni-processor, graphics off,
      and certain IO devices in the SC must be off.  If those pre-conditions
      are met, then the PMU allows cpuidle to enter S0i3, otherwise such requests
      are demoted, either to Atom C4 or Atom C6.
      This driver is based on prototype work by Bruce Flemming,
      Illyas Mansoor, Rajeev D. Muralidhar, Vishwesh M. Rudramuni,
      Hari Seshadri and Sujith Thomas.  The current driver also
      includes contributions from H. Peter Anvin, Arjan van de Ven,
      Kristen Accardi, and Yong Wang.
      Thanks for additional review feedback from Alan Cox and Randy Dunlap.
      Acked-by: default avatarAlan Cox <alan@linux.intel.com>
      Acked-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
  3. 02 Aug, 2011 1 commit
  4. 01 Aug, 2011 2 commits
  5. 29 Jul, 2011 1 commit
    • Dominik Brodowski's avatar
      cpupowerutils - cpufrequtils extended with quite some features · 7fe2f639
      Dominik Brodowski authored
      CPU power consumption vs performance tuning is no longer
      limited to CPU frequency switching anymore: deep sleep states,
      traditional dynamic frequency scaling and hidden turbo/boost
      frequencies are tied close together and depend on each other.
      The first two exist on different architectures like PPC, Itanium and
      ARM, the latter (so far) only on X86. On X86 the APU (CPU+GPU) will
      only run most efficiently if CPU and GPU has proper power management
      in place.
      Users and Developers want to have *one* tool to get an overview what
      their system supports and to monitor and debug CPU power management
      in detail. The tool should compile and work on as many architectures
      as possible.
      Once this tool stabilizes a bit, it is intended to replace the
      Intel-specific tools in tools/power/x86
      Signed-off-by: default avatarDominik Brodowski <linux@dominikbrodowski.net>
  6. 28 Jul, 2011 3 commits
  7. 27 Jul, 2011 1 commit
  8. 25 Jul, 2011 2 commits
  9. 23 Jul, 2011 1 commit
    • Mark Brown's avatar
      regmap: Add generic non-memory mapped register access API · b83a313b
      Mark Brown authored
      There are many places in the tree where we implement register access for
      devices on non-memory mapped buses, especially I2C and SPI. Since hardware
      designers seem to have settled on a relatively consistent set of register
      interfaces this can be effectively factored out into shared code.  There
      are a standard set of formats for marshalling data for exchange with the
      device, with the actual I/O mechanisms generally being simple byte
      We create an abstraction for marshaling data into formats which can be
      sent on the control interfaces, and create a standard method for
      plugging in actual transport underneath that.
      This is mostly a refactoring and renaming of the bottom level of the
      existing code for sharing register I/O which we have in ASoC. A
      subsequent patch in this series converts ASoC to use this.  The main
      difference in interface is that reads return values by writing to a
      location provided by a pointer rather than in the return value, ensuring
      we can use the full range of the type for register data.  We also use
      unsigned types rather than ints for the same reason.
      As some of the devices can have very large register maps the existing
      ASoC code also contains infrastructure for managing register caches.
      This cache work will be moved over in a future stage to allow for
      separate review, the current patch only deals with the physical I/O.
      Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
      Acked-by: default avatarLiam Girdwood <lrg@ti.com>
      Acked-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
      Acked-by: default avatarWolfram Sang <w.sang@pengutronix.de>
      Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
  10. 22 Jul, 2011 2 commits
  11. 21 Jul, 2011 1 commit
  12. 20 Jul, 2011 2 commits
  13. 18 Jul, 2011 1 commit
  14. 15 Jul, 2011 1 commit
  15. 13 Jul, 2011 1 commit
  16. 12 Jul, 2011 2 commits
  17. 08 Jul, 2011 1 commit
  18. 07 Jul, 2011 1 commit
  19. 06 Jul, 2011 1 commit
  20. 05 Jul, 2011 13 commits