1. 23 Jan, 2008 5 commits
    • Tejun Heo's avatar
      ahci: factor out AHCI enabling and enable AHCI before reading CAP · b710a1f4
      Tejun Heo authored
      
      
      Factor out AHCI enabling into ahci_enable_ahci() and enabling AHCI
      before reading CAP in ahci_save_initial_config() as the spec requires
      enabling AHCI mode before accessing any other registers.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      b710a1f4
    • Al Viro's avatar
      libata annotations and fixes · 4ca4e439
      Al Viro authored
      
      Signed-off-by: default avatarAl Viro <viro@zeniv.linux.org.uk>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      4ca4e439
    • Tejun Heo's avatar
      libata: convert to chained sg · ff2aeb1e
      Tejun Heo authored
      
      
      libata used private sg iterator to handle padding sg.  Now that sg can
      be chained, padding can be handled using standard sg ops.  Convert to
      chained sg.
      
      * s/qc->__sg/qc->sg/
      
      * s/qc->pad_sgent/qc->extra_sg[]/.  Because chaining consumes one sg
        entry.  There need to be two extra sg entries.  The renaming is also
        for future addition of other extra sg entries.
      
      * Padding setup is moved into ata_sg_setup_extra() which is organized
        in a way that future addition of other extra sg entries is easy.
      
      * qc->orig_n_elem is unused and removed.
      
      * qc->n_elem now contains the number of sg entries that LLDs should
        map.  qc->mapped_n_elem is added to carry the original number of
        mapped sgs for unmapping.
      
      * The last sg of the original sg list is used to chain to extra sg
        list.  The original last sg is pointed to by qc->last_sg and the
        content is stored in qc->saved_last_sg.  It's restored during
        ata_sg_clean().
      
      * All sg walking code has been updated.  Unnecessary assertions and
        checks for conditions the core layer already guarantees are removed.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: Jens Axboe <jens.axboe@oracle.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      ff2aeb1e
    • Tejun Heo's avatar
      libata: implement protocol tests · 405e66b3
      Tejun Heo authored
      
      
      Implement protocol tests - ata_is_atapi(), ata_is_nodata(),
      ata_is_pio(), ata_is_dma(), ata_is_ncq() and ata_is_data() and use
      them to replace is_atapi_taskfile() and hard coded protocol tests.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      405e66b3
    • Tejun Heo's avatar
      ahci: update PCS programming · 49f29090
      Tejun Heo authored
      
      
      For intel ones, ahci unconditionally OR'd 0xf to PCS.  This isn't
      correct for the following cases.
      
      * ich6/7m's which only implement P0 and P2 (0xf works fine tho)
      
      * ich8/9's which have six ports and needs 0x3f to enable all ports
      
      This patch updates PCS programming such that...
      
      * port_map determined by ahci_save_initial_config() is OR'd instead of 0xf
      
      * PCS is updated only if necessary (there are turned off enable bits)
      
      port_map is determined from PORTS_IMPL PCI register which is
      implemented as write or write-once register.  If the register isn't
      programmed, ahci automatically generates it from number of ports,
      which is good enough for PCS programming.  ICH6/7M are probably the
      only ones where non-contiguous enable bits are necessary && PORTS_IMPL
      isn't programmed properly but they're proven to work reliably with 0xf
      anyway.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      49f29090
  2. 07 Dec, 2007 3 commits
    • Tejun Heo's avatar
      libata: kill spurious NCQ completion detection · 459ad688
      Tejun Heo authored
      Spurious NCQ completion detection implemented in ahci was incorrect.
      On AHCI receving and processing FISes and raising interrupts are not
      interlocked and spurious interrupts are expected.
      
      For example, if an interrupt occurs while interrupt handler is running
      and the running interrupt handler handles the event the new IRQ
      indicated, after IRQ handler finishes, it will be executed again
      because IRQ pending bit is set by the new interrupt but there won't be
      anything to process.
      
      Please read the following message for more information.
      
        http://article.gmane.org/gmane.linux.ide/26012
      
      This patch...
      
      * Removes all spurious IRQ whining from ahci.  Spurious NCQ completion
        detection was completely wrong.  Spurious D2H Register FIS taught us
        that some early drives send spurious D2H Register FIS with I bit set
        while NCQ commands are in progress but none of recent drives does
        that and even the ones which show such behavior can do NCQ fine.
      
      * Kills all NCQ blacklist entries which were added because of spurious
        NCQ completions.  I tracked down each commit and verified all
        removed ones are actually added because of spurious completions.
      
        WD740ADFD-00NLR1 wasn't deleted but moved upward because the drive
        not only had spurious NCQ completions but also is slow on sequential
        data transfers if NCQ is enabled.
      
        Maxtor 7V300F0 was added by 0e3dbc01
      
      
        from Alan Cox.  I can only find evidences that the drive only had
        troubles with spuruious completions by searching the mailing list.
        This entry needs to be verified and removed if it doesn't have other
        NCQ related problems.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      459ad688
    • Tejun Heo's avatar
      ahci: don't attach if ICH6 is in combined mode · c4f7792c
      Tejun Heo authored
      
      
      ICH6 R/Ms share PCI ID between piix and ahci modes and we've been
      allowing ahci to attach regardless of how BIOS configured it.
      However, enabling AHCI mode when the controller is in combined mode
      can result in unexpected behavior.  Don't attach if the controller is
      in combined mode.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: Bill Nottingham <notting@redhat.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      c4f7792c
    • Tejun Heo's avatar
      ahci: fix engine reset failed message · 994056d7
      Tejun Heo authored
      
      
      There isn't much point in reporting -EOPNOTSUPP as failure.  Also the
      message was missing newline.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      994056d7
  3. 04 Dec, 2007 1 commit
  4. 29 Oct, 2007 3 commits
    • Kristen Carlson Accardi's avatar
      [libata] AHCI: add hw link power management support · 31556594
      Kristen Carlson Accardi authored
      
      
      This patch will set the correct bits to turn on Aggressive
      Link Power Management (ALPM) for the ahci driver.  This
      will cause the controller and disk to negotiate a lower
      power state for the link when there is no activity (see
      the AHCI 1.x spec for details).  This feature is mutually
      exclusive with Hot Plug, so when ALPM is enabled, Hot Plug
      is disabled.  ALPM will be enabled by default, but it is
      settable via the scsi host syfs interface.  Possible
      settings for this feature are:
      
      Setting         Effect
      ----------------------------------------------------------
      min_power       ALPM is enabled, and link set to enter
                      lowest power state (SLUMBER) when idle
                      Hot plug not allowed.
      
      max_performance ALPM is disabled, Hot Plug is allowed
      
      medium_power    ALPM is enabled, and link set to enter
                      second lowest power state (PARTIAL) when
                      idle.  Hot plug not allowed.
      Signed-off-by: default avatarKristen Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
      31556594
    • Jeff Garzik's avatar
      [libata] AHCI: fix newly introduced host-reset bug · ab6fc95f
      Jeff Garzik authored
      
      
      The recent fix to host reset introduced a problem, whereby AHCI-enable
      bit would be cleared upon reset, if it was not asserted prior to reset.
      
      Unconditionally enable AHCI-enable bit.
      Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
      ab6fc95f
    • Tejun Heo's avatar
      libata: implement ata_wait_after_reset() · 88ff6eaf
      Tejun Heo authored
      
      
      On certain device/controller combination, 0xff status is asserted
      after reset and doesn't get cleared during 150ms post-reset wait.  As
      0xff status is interpreted as no device (for good reasons), this can
      lead to misdetection on such cases.
      
      This patch implements ata_wait_after_reset() which replaces the 150ms
      sleep and waits upto ATA_TMOUT_FF_WAIT if status is 0xff.
      ATA_TMOUT_FF_WAIT is currently 800ms which is enough for
      HHD424020F7SV00 to get detected but not enough for Quantum GoVault
      drive which is known to take upto 2s.
      
      Without parallel probing, spending 2s on 0xff port would incur too
      much delay on ata_piix's which use 0xff to indicate empty port and
      doesn't have SCR register, so GoVault needs to wait till parallel
      probing.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      88ff6eaf
  5. 25 Oct, 2007 1 commit
    • Tejun Heo's avatar
      ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2 · edc93052
      Tejun Heo authored
      P5W-DH Deluxe has ICH9 which doesn't have PMP support but SIMG 4726
      hardwired to the second port of AHCI controller at PCI device 1f.2.
      The 4726 doesn't work as PMP but as a storage processor which can do
      hardware RAID on downstream ports.
      
      When no device is attached to the downstream port of the 4726, pseudo
      ATA device for configuration appears.  Unfortunately, ATA emulation on
      the device is very lousy and causes long hang during boot.
      
      This patch implements workaround for the board.  If the mainboard is
      P5W-DH Deluxe (matched using DMI), only hardreset is used on the
      second port of AHCI controller @ 1f.2 and the hardreset doesn't depend
      on receiving the first FIS and just proceed to IDENTIFY.
      
      This workaround fixes bugzilla #8923.
      
        http://bugzilla.kernel.org/show_bug.cgi?id=8923
      
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      edc93052
  6. 23 Oct, 2007 1 commit
  7. 19 Oct, 2007 1 commit
  8. 12 Oct, 2007 23 commits
    • Tejun Heo's avatar
      libata: use ata_exec_internal() for PMP register access · b06ce3e5
      Tejun Heo authored
      
      
      PMP registers used to be accessed with dedicated accessors ->pmp_read
      and ->pmp_write.  During reset, those callbacks are called with the
      port frozen so they should be able to run without depending on
      interrupt delivery.  To achieve this, they were implemented polling.
      
      However, as resetting the host port makes the PMP to isolate fan-out
      ports until SError.X is cleared, resetting fan-out ports while port is
      frozen doesn't buy much additional safety.
      
      This patch updates libata PMP support such that PMP registers are
      accessed using regular ata_exec_internal() mechanism and kills
      ->pmp_read/write() callbacks.  The following changes are made.
      
      * PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(),
        sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which
        are now standalone PMP register access functions.
      
      * sata_pmp_read/write() returns err_mask instead of rc.  This is
        consistent with other functions which issue internal commands and
        allows more detailed error reporting.
      
      * ahci interrupt handler is modified to ignore BAD_PMP and
        spurious/illegal completion IRQs while reset is in progress.  These
        conditions are expected during reset.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      b06ce3e5
    • Tejun Heo's avatar
      ahci: fix notification handling · 5f226c6b
      Tejun Heo authored
      
      
      Asynchronous notification on ICH9 didn't work because it didn't write
      AN FIS into the RX area - it only updates SNotification.  Also,
      snooping SDB_FIS RX area is racy against further SDB FIS receptions.
      Let sata_async_notification() determine using SNTF if it's available
      and snoop RX area iff SNTF isn't available
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      5f226c6b
    • Tejun Heo's avatar
      ahci: clean up PORT_IRQ_BAD_PMP enabling · 1c954a4d
      Tejun Heo authored
      
      
      Now that we have pp->intr_mask, move PORT_IRQ_BAD_PMP enabling to
      ahci_pmp_attach/detach() where it belongs.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      1c954a4d
    • Tejun Heo's avatar
      ahci: kill leftover from enabling NCQ over PMP · 75da6d2b
      Tejun Heo authored
      
      
      ahci had problems with NCQ over PMP and NCQ used to be disabled while
      PMP was attached.  After fixing the problem, the temporary NCQ
      disabling code wasn't removed completely.  Kill the remaining piece.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      75da6d2b
    • Peer Chen's avatar
      ahci: Add MCP79 support to AHCI driver · 7100819f
      Peer Chen authored
      
      Signed-off-by: default avatarPeer Chen <peerchen@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      7100819f
    • Tejun Heo's avatar
      ahci: implement AHCI_HFLAG_NO_PMP · 6949b914
      Tejun Heo authored
      
      
      Of course some controllers lie about PMP support.  Black list them.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      6949b914
    • Tejun Heo's avatar
      ahci: move host flags over to pi.private_data · 417a1a6d
      Tejun Heo authored
      
      
      Private pi.flags area is full and we need more private flags.  Move
      host private flags over to pi.private_data.  During initialization,
      these flags are copied to hpriv->flags.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      417a1a6d
    • Tejun Heo's avatar
      ahci: implement PMP support · 7d50b60b
      Tejun Heo authored
      
      
      Implement AHCI PMP support.  ahci only supports command based
      switching.  Also, for some reason, NCQ over PMP doesn't work now.
      Other than that, everything works.
      
      Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: Forrest Zhao <forrest.zhao@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      7d50b60b
    • Jeff Garzik's avatar
      [libata] AHCI: enable AHCI mode, before using AHCI reset · 3cc3eb11
      Jeff Garzik authored
      
      
      AHCI spec says host-reset bit may only be set when the ahci-enable bit
      is also set.
      
      Noticed by Peer Chen <peerchen@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      3cc3eb11
    • Tejun Heo's avatar
      libata-pmp-prep: implement sata_async_notification() · 7d77b247
      Tejun Heo authored
      
      
      AN serves multiple purposes.  For ATAPI, it's used for media change
      notification.  For PMP, for downstream PHY status change notification.
      Implement sata_async_notification() which demultiplexes AN.
      
      To avoid unnecessary port events, ATAPI AN is not enabled if PMP is
      attached but SNTF is not available.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: Kriten Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      7d77b247
    • Tejun Heo's avatar
      libata-pmp-prep: implement ops->qc_defer() · 31cc23b3
      Tejun Heo authored
      
      
      Controllers which support PMP have various restrictions on which
      combinations of commands are allowed to what number of devices
      concurrently.  This patch implements ops->qc_defer() which determines
      whether a qc can be issued at the moment or should be deferred.
      
      If the function returns ATA_DEFER_LINK, the qc will be deferred until
      a qc completes on the link.  If ATA_DEFER_PORT, until a qc completes
      on any link.  The defer conditions are advisory and in general
      ATA_DEFER_LINK can be considered as lower priority deferring than
      ATA_DEFER_PORT.
      
      ops->qc_defer() replaces fixed ata_scmd_need_defer().  For standard
      NCQ/non-NCQ exclusion, ata_std_qc_defer() is implemented.  ahci and
      sata_sil24 are converted to use ata_std_qc_defer().
      
      ops->qc_defer() is heavier than the original mechanism because full qc
      is prepped before determining to defer it, but various information is
      needed to determine defer conditinos and fully translating a qc is the
      only way to supply such information in generic manner.
      
      IMHO, this shouldn't cause any noticeable performance issues as
      
      * for most cases deferring occurs rarely (except for NCQ-aware
        cmd-switching PMP)
      * translation itself isn't that expensive
      * once deferred the command won't be repeated until another command
        completes which usually is a very long time cpu-wise.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      31cc23b3
    • Tejun Heo's avatar
      libata: misc updates for AN · 854c73a2
      Tejun Heo authored
      
      
      Update AN support in preparation of PMP support.
      
      * s/ata_id_has_AN/ata_id_has_atapi_AN/
      * add AN enabled reporting during configuration
      * add err_mask to AN configuration failure reporting
      * update LOCKING comment for ata_scsi_media_change_notify()
      * check whether ATA dev is attached to SCSI dev ata_scsi_media_change_notify()
      * set ATA_FLAG_AN in ahci and sata_sil24
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: Kriten Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      854c73a2
    • Jason Gaston's avatar
      d4155e6f
    • Tejun Heo's avatar
      ahci: reimplement port_map handling · 7a234aff
      Tejun Heo authored
      
      
      Reimplement port_map handling such that
      
      1. Non-zero PORTS_IMPL value is always examined and used if consistent
         with cap.n_ports.
      
      2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and
         force port_map to be ((1 << cap.n_ports) - 1).
      
      3. There were two separate places dealing with port_map.  Unify them
         to one.
      
      As all newer ahci chips seem to get PI correct and older ones usually
      have zero PI.  Controllers with holes in PI are very unlikely to screw
      up PI, so #2 makes more sense than following inconsistent PI.
      
      Without this change, not setting ATA_FLAG_HONOR_PI when it's needed
      results in weird detection failure.  This changed logic should be able
      to handle all known cases correctly automatically.
      
      Verified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9,
      JMB360 and JMB363.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      7a234aff
    • Tejun Heo's avatar
      libata: implement and use ata_port_desc() to report port configuration · cbcdd875
      Tejun Heo authored
      
      
      Currently, port configuration reporting has the following problems.
      
      * iomapped address is reported instead of raw address
      * report contains irrelevant fields or lacks necessary fields for
        non-SFF controllers.
      * host->irq/irq2 are there just for reporting and hacky.
      
      This patch implements and uses ata_port_desc() and
      ata_port_pbar_desc().  ata_port_desc() is almost identical to
      ata_ehi_push_desc() except that it takes @ap instead of @ehi, has no
      locking requirement, can only be used during host initialization and "
      " is used as separator instead of ", ".  ata_port_pbar_desc() is a
      helper to ease reporting of a PCI BAR or an offsetted address into it.
      
      LLD pushes whatever description it wants using the above two
      functions.  The accumulated description is printed on host
      registration after "[S/P]ATA max MAX_XFERMODE ".
      
      SFF init helpers and ata_host_activate() automatically add
      descriptions for addresses and irq respectively, so only LLDs which
      isn't standard SFF need to add custom descriptions.  In many cases,
      such controllers need to report different things anyway.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      cbcdd875
    • Jeff Garzik's avatar
      [libata] Remove ->port_disable() hook · ac8869d5
      Jeff Garzik authored
      
      
      It was always set to ata_port_disable().  Removed the hook, and replaced
      the very few ap->ops->port_disable() callsites with direct calls to
      ata_port_disable().
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      ac8869d5
    • Jeff Garzik's avatar
      [libata] Remove ->irq_ack() hook, and ata_dummy_irq_on() · 6d32d30f
      Jeff Garzik authored
      
      
      * ->irq_ack() is redundant to what the irq handler already
        performs... chk-status + irq-clear.  Furthermore, it is only
        called in one place, when screaming-irq-debugging is enabled,
        so we don't want to bother with a hook just for that.
      
      * ata_dummy_irq_on() is only ever used in drivers that have
        no callpath reaching ->irq_on().  Remove .irq_on hook from
        those drivers, and the now-unused ata_dummy_irq_on()
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      6d32d30f
    • Kristen Carlson Accardi's avatar
      ahci: Store interrupt value · a7384925
      Kristen Carlson Accardi authored
      
      
      Use a stored value for which interrupts to enable.  Changing this allows
      us to selectively turn off certain interrupts later and have them
      stay off.
      Signed-off-by: default avatarKristen Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      a7384925
    • Kristen Carlson Accardi's avatar
      [libata] ahci: send event when AN received · 2f294968
      Kristen Carlson Accardi authored
      
      
      When we get an SDB FIS with the 'N' bit set, we should send
      an event to user space to indicate that there has been a
      media change.  This will be done via the scsi device.
      Signed-off-by: default avatarKristen Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      2f294968
    • Tejun Heo's avatar
      libata-link: make two port flags HRST_TO_RESUME and SKIP_D2H_BSY link flags · 0c88758b
      Tejun Heo authored
      
      
      HRST_TO_RESUME and SKIP_D2H_BSY are link attributes.  Move them to
      ata_link->flags.  This will allow host and PMP links to have different
      attributes.  ata_port_info->link_flags is added and used by LLDs to
      specify these flags during initialization.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      0c88758b
    • Tejun Heo's avatar
      libata-link: linkify reset · cc0680a5
      Tejun Heo authored
      
      
      Make reset methods and related functions deal with ata_link instead of
      ata_port.
      
      * ata_do_reset()
      * ata_eh_reset()
      * all prereset/reset/postreset methods and related functions
      
      This patch introduces no behavior change.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      cc0680a5
    • Tejun Heo's avatar
      libata-link: linkify PHY-related functions · 936fd732
      Tejun Heo authored
      
      
      Make the following PHY-related functions to deal with ata_link instead
      of ata_port.
      
      * sata_print_link_status()
      * sata_down_spd_limit()
      * ata_set_sata_spd_limit() and friends
      * sata_link_debounce/resume()
      * sata_scr_valid/read/write/write_flush()
      * ata_link_on/offline()
      
      This patch introduces no behavior change.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      936fd732
    • Tejun Heo's avatar
      libata-link: introduce ata_link · 9af5c9c9
      Tejun Heo authored
      
      
      Introduce ata_link.  It abstracts PHY and sits between ata_port and
      ata_device.  This new level of abstraction is necessary to support
      SATA Port Multiplier, which basically adds a bunch of links (PHYs) to
      a ATA host port.  Fields related to command execution, spd_limit and
      EH are per-link and thus moved to ata_link.
      
      This patch only defines the host link.  Multiple link handling will be
      added later.  Also, a lot of ap->link derefences are added but many of
      them will be removed as each part is converted to deal directly with
      ata_link instead of ata_port.
      
      This patch introduces no behavior change.
      Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
      Cc: James Bottomley <James.Bottomley@SteelEye.com>
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      9af5c9c9
  9. 20 Sep, 2007 1 commit
  10. 20 Jul, 2007 1 commit
    • su henry's avatar
      The SATA controller device ID is different according to · badc2341
      su henry authored
      
      the onchip SATA type set in the system BIOS:
      Device                              Device ID
      SATA in IDE mode             0x4390
      SATA in AHCI mode           0x4391
      SATA in non-raid5 driver     0x4392
      SATA in raid5 driver           0x4393
      
      Although the device ID is different, they use the same AHCI driver
      .The attached file is the patch for adding these device
      IDs for ATI SB700.
      
      Signed-off-by: henry.su.ati@gmail.com
      Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
      badc2341