1. 06 Feb, 2011 1 commit
  2. 13 Oct, 2010 1 commit
  3. 13 Jul, 2010 1 commit
  4. 24 Aug, 2009 1 commit
  5. 19 Aug, 2009 3 commits
  6. 12 Feb, 2009 2 commits
    • Kumar Gala's avatar
      powerpc/book-3e: Introduce concept of Book-3e MMU · 70fe3af8
      Kumar Gala authored
      
      
      The Power ISA 2.06 spec introduces a standard MMU programming model that
      is based on the Freescale Book-E MMU programing model.  The Freescale
      version is pretty backwards compatiable with the ISA 2.06 definition so
      we are starting to refactor some of the Freescale code so it can be
      easily shared.
      
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      70fe3af8
    • Kumar Gala's avatar
      powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines · d66c82ea
      Kumar Gala authored
      
      
      The Power ISA 2.06 added power of two page sizes to the embedded MMU
      architecture.  Its done it such a way to be code compatiable with the
      existing HW.  Made the minor code changes to support both power of two
      and power of four page sizes.  Also added some new MAS bits and macros
      that are defined as part of the 2.06 ISA.  Renamed some things to use
      the 'Book-3e' concept to convey the new MMU that is based on the
      Freescale Book-E MMU programming model.
      
      Note, its still invalid to try and use a page size that isn't supported
      by cpu.
      
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      d66c82ea
  7. 20 Dec, 2008 1 commit
    • Benjamin Herrenschmidt's avatar
      powerpc/mm: Rework context management for CPUs with no hash table · 2ca8cf73
      Benjamin Herrenschmidt authored
      
      
      This reworks the context management code used by 4xx,8xx and
      freescale BookE.  It adds support for SMP by implementing a
      concept of stale context map to lazily flush the TLB on
      processors where a context may have been invalidated.  This
      also contains the ground work for generalizing such lazy TLB
      flushing by just picking up a new PID and marking the old one
      stale.  This will be implemented later.
      
      This is a first implementation that uses a global spinlock.
      
      Ideally, we should try to get at least the fast path (context ID
      already assigned) lockless or limited to a per context lock,
      but for now this will do.
      
      I tried to keep the UP case reasonably simple to avoid adding
      too much overhead to 8xx which does a lot of context stealing
      since it effectively has only 16 PIDs available.
      
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      2ca8cf73
  8. 03 Dec, 2008 1 commit
    • Trent Piepho's avatar
      powerpc: Better setup of boot page TLB entry · b3898895
      Trent Piepho authored
      
      
      The initial TLB mapping for the kernel boot didn't set the memory coherent
      attribute, MAS2[M], in SMP mode.
      
      If this code supported booting a secondary processor, which it doesn't yet,
      but if it did, then when a secondary processor boots, it would probably signal
      the primary processor by setting a variable called something like
      __secondary_hold_acknowledge.  However, due to the lack of the M bit, the
      primary processor would not snoop the transaction (even if a transaction were
      broadcast).  If primary CPU's L1 D-cache had a copy, it would not be flushed
      and the CPU would never see the ack.  Which would have resulted in the primary
      CPU spinning for a long time, perhaps a full second before it gives up, while
      it would have waited for the ack from the secondary CPU that it wouldn't have
      been able to see because of the stale cache.
      
      The value of MAS2 for the boot page TLB1 entry is a compile time constant,
      so there is no need to calculate it in powerpc assembly language.
      
      Also, from the MPC8572 manual section 6.12.5.3, "Bits that represent
      offsets within a page are ignored and should be cleared." Existing code
      didn't clear them, this code does.
      
      The same when the page of KERNELBASE is found; we don't need to use asm to
      mask the lower 12 bits off.
      
      In the code that computes the address to rfi from, don't hard code the
      offset to 24 bytes, but have the assembler figure that out for us.
      
      Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      b3898895
  9. 03 Aug, 2008 1 commit
  10. 16 Apr, 2008 1 commit
    • Kumar Gala's avatar
      [POWERPC] Move phys_addr_t definition into asm/types.h · d04ceb3f
      Kumar Gala authored
      
      
      Moved phys_addr_t out of mmu-*.h and into asm/types.h so we can use it in
      places that before would have caused recursive includes.
      
      For example to use phys_addr_t in <asm/page.h> we would have included
      <asm/mmu.h> which would have possibly included <asm/mmu-hash64.h> which
      includes <asm/page.h>.  Wheeee recursive include.
      
      CONFIG_PHYS_64BIT is a bit counterintuitive in light of ppc64 systems
      and thus the config option is only used for ppc32 systems with >32-bit
      physical addresses (44x, 85xx, 745x, etc.).
      
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      d04ceb3f
  11. 03 Jul, 2007 1 commit