1. 30 Jun, 2016 2 commits
  2. 29 Jun, 2016 2 commits
  3. 28 Jun, 2016 3 commits
  4. 22 Jun, 2016 15 commits
  5. 21 Jun, 2016 7 commits
  6. 20 Jun, 2016 11 commits
    • Stephen Boyd's avatar
      Merge tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung into clk-next · b6f4f1f2
      Stephen Boyd authored
      Merge changes from Sylwester Nawrocki for samsung clk drivers:
      
       - a fix for exynos7 to prevent gating some critical CMU clocks,
       - addition of CPU clocks for CPU frequency scaling on Exynos5433 SoCs,
       - additions for exynos5410 SoC required for Odroid XU board support,
       - register accessors fixes for kernels built for big endian operation
         (mostly exynos4 SoCs),
       - Exynos5433 clock definitions fixes required for suspend to RAM and
         the audio subsystem operation,
       - many cleanups changing attributes of the clock initializer data
      
      * tag 'clk-samsung-4.8' of git://linuxtv.org/snawrocki/samsung: (41 commits)
        clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE device
        clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2R
        clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UART
        clk: samsung: exynos4: fixup reg access on be
        clk: samsung: fixup endian in pll clk
        clk: samsung: exynos5410: Add WDT, ACLK266 and SSS clocks
        clk: samsung: exynos5433: add CPU clocks configuration data and instantiate CPU clocks
        clk: samsung: cpu: prepare for adding Exynos5433 CPU clocks
        clk: samsung: exynos5433: prepare for adding CPU clocks
        clk: samsung: Suppress unbinding to prevent theoretical attacks
        clk: samsung: exynos5420: Set ID for aclk333 gate clock
        clk: samsung: exynos5410: Add TMU clock
        clk: samsung: exynos5410: Add I2C, HSI2C and RTC clocks
        clk: samsung: exynos5410: Add serial3, USB and PWM clocks
        clk: samsung: exynos3250: Move PLL rates data to init section
        clk: samsung: Fully constify mux parent names
        clk: samsung: exynos5250: Move sleep init function to init section
        clk: samsung: exynos5420: Move sleep init function and PLL data to init section
        clk: samsung: exynos5433: Move PLL rates data to init section
        clk: samsung: exynos5433: Constify all clock initializers
        ...
      b6f4f1f2
    • Peng Fan's avatar
      clk: correct comments for __clk_determine_rate · 2d5b520c
      Peng Fan authored
      Correct comments for __clk_determine_rate.
      Signed-off-by: default avatarPeng Fan <van.freenix@gmail.com>
      Cc: Michael Turquette <mturquette@baylibre.com>
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      2d5b520c
    • Roman Volkov's avatar
      clk: vt8500: rework wm8650_find_pll_bits() · c03d795b
      Roman Volkov authored
      PLL clock on WM8650 is calculated in the following way:
      
      M * parent [O1] => / P [O2] => / D [O3]
      
      Where O2 is 600MHz >= (M * parent) / P >= 300MHz.
      
      Current algorithm does not met this requirement, so that the
      function may return rates which are not supported by the hardware.
      
      This patch fixes the algorithm and simplifies the code, reducing
      the calculation time by ~10000 times (according to usermode app) by
      removing the nested loops.
      Signed-off-by: default avatarRoman Volkov <rvolkov@v1ros.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      c03d795b
    • Arnd Bergmann's avatar
      clk: vt8500: fix gcc-4.9 warnings · 27a0becc
      Arnd Bergmann authored
      This fixes some false positive warnings we get with older compiler
      versions:
      
      clk-vt8500.c: In function ‘wm8650_find_pll_bits’:
      clk-vt8500.c:430:12: ‘best_div2’ may be used uninitialized in this function
      clk-vt8500.c:429:12: ‘best_div1’ may be used uninitialized in this function
      clk-vt8500.c:428:14: ‘best_mul’ may be used uninitialized in this function
      clk-vt8500.c: In function ‘wm8750_find_pll_bits’:
      clk-vt8500.c:509:12: ‘best_div2’ may be used uninitialized in this function
      clk-vt8500.c:508:12: ‘best_div1’ may be used uninitialized in this function
      clk-vt8500.c:507:14: ‘best_mul’ may be used uninitialized in this function
      clk-vt8500.c: In function ‘wm8850_find_pll_bits’:
      clk-vt8500.c:560:12: ‘best_div2’ may be used uninitialized in this function
      clk-vt8500.c:559:12: ‘best_div1’ may be used uninitialized in this function
      clk-vt8500.c:558:14: ‘best_mul’ may be used uninitialized in this function
      
      As the local variables are only use for temporaries, we can just
      as well assign the final values directly, which also makes the
      code slightly shorter.
      Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarRoman Volkov <rvolkov@v1ros.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      27a0becc
    • Lee Jones's avatar
      clk: Remove unused variable · 06b37e4a
      Lee Jones authored
      Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      06b37e4a
    • Ben Dooks's avatar
      clk: hi6220: fix missing clk.h include · b62c190f
      Ben Dooks authored
      Fix the warning from missing "clk.h" include which
      defines hi6220_register_clkdiv() function.
      
      drivers/clk/hisilicon/clkdivider-hi6220.c:102:12: warning: symbol 'hi6220_register_clkdiv' was not declared. Should it be static?
      Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      b62c190f
    • Ben Dooks's avatar
      clk: iproc: fix missing include of clk-iproc.h · c895db85
      Ben Dooks authored
      Fix the implicit declaration of iproc_armpll_setup() by
      including clk-iproc.h which defines it. Fixes the warning:
      
      drivers/clk/bcm/clk-iproc-armpll.c:242:13: warning: symbol 'iproc_armpll_setup' was not declared. Should it be static?
      Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
      Acked-by: default avatarRay Jui <ray.jui@broadcom.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      c895db85
    • Ben Dooks's avatar
      clk: at91: make of_sama5d2_clk_generated_setup() static · 14755549
      Ben Dooks authored
      The of_sama5d2_clk_generated_setup() is not exported outside
      of the driver, so make it static to fix the warning about it
      being not static:
      
      drivers/clk/at91/clk-generated.c:270:13: warning: symbol 'of_sama5d2_clk_generated_setup' was not declared. Should it be static?
      Signed-off-by: default avatarBen Dooks <ben.dooks@codethink.co.uk>
      Acked-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      14755549
    • Stephen Boyd's avatar
      Merge branch 'clk-fixes' into clk-next · dd6c1331
      Stephen Boyd authored
      * clk-fixes:
        clk: Fix return value check in oxnas_stdclk_probe()
        clk: rockchip: release io resource when failing to init clk on rk3399
        clk: rockchip: fix cpuclk registration error handling
        clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization"
        clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
        clk: rockchip: mark rk3399 GIC clocks as critical
        clk: rockchip: initialize flags of clk_init_data in mmc-phase clock
      dd6c1331
    • Stephen Boyd's avatar
      Merge tag 'v4.7-rockchip-clk-fixes1' of... · 08634770
      Stephen Boyd authored
      Merge tag 'v4.7-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes
      
      A bunch of fixes. Some for the newly added rk3399 clock tree, some
      concerning error handling and initialization and a revert of the
      mmc-phase clock initialization, as this could conflict with the
      bootloader setting of this clock and a real solution to initing
      the phase correctly from dw_mmc went in as fix for 4.7 through
      the mmc tree.
      
      * tag 'v4.7-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
        clk: rockchip: release io resource when failing to init clk on rk3399
        clk: rockchip: fix cpuclk registration error handling
        clk: rockchip: Revert "clk: rockchip: reset init state before mmc card initialization"
        clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
        clk: rockchip: mark rk3399 GIC clocks as critical
        clk: rockchip: initialize flags of clk_init_data in mmc-phase clock
      08634770
    • Wei Yongjun's avatar
      clk: Fix return value check in oxnas_stdclk_probe() · a5e9b85a
      Wei Yongjun authored
      In case of error, the function syscon_node_to_regmap() returns
      ERR_PTR() and never returns NULL. The NULL test in the return
      value check should be replaced with IS_ERR().
      Signed-off-by: default avatarWei Yongjun <yongjun_wei@trendmicro.com.cn>
      Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
      Fixes: 0bbd72b4 ("clk: Add Oxford Semiconductor OXNAS Standard Clocks")
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      a5e9b85a