1. 16 Feb, 2007 4 commits
  2. 07 Feb, 2007 9 commits
    • Sergei Shtylyov's avatar
      hpt366: HPT36x PCI clock detection fix · 6273d26a
      Sergei Shtylyov authored
      Fix minor coding mistake in the HPT36x PCI clock detection code noticed by
      Bartlomiej Zolnierkiewicz -- it always reported 33 MHz due to the missing
      'break' statements.  This, however, most probably never mattered -- in fact, I
      was thinking of removing the 25/40 MHz cases completely since HPT36x BIOSes
      didn't seem to set any other value than 7 into the 'cmd_high_time' field, i.e.
       supported only 33 MHz PCI.
      
      Note that in the original driver there was another bug: 25 and 40 MHz cases
      were interchanged.  Since the 'cmd_high_time' field is in units of PCI clocks,
      a lower clock count just *cannot* correspond to a higher frequency, i.  e.  it
      should be 5 for 25 MHz PCI and 9 for 40 MHz PCI, not the other way around.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      6273d26a
    • Sergei Shtylyov's avatar
      hpt366: init code rewrite · 7b73ee05
      Sergei Shtylyov authored
      Finally, rework the driver init.  code to correctly handle all the chip
      variants HighPoint has created so far.  This should cure the rest of the
      timing issues in the driver (especially, on 66 MHz PCI) caused by the
      HighPoint's habit of switching the base DPLL clock with every new revision
      of the chips...
      
        - switch to using the enumeration type to differ between the numerous chip
          variants, matching PCI device/revision ID with the chip type early, at the
          init_setup stage;
      
        - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
          stop duplicating it for each channel by storing the pointer in the pci_dev
          structure: first, at the init_setup stage, point it to a static "template"
          with only the chip type and its specific base DPLL frequency, the highest
          supported DMA mode, and the chip settings table pointer filled, then, at
          the init_chipset stage, allocate per-chip instance  and fill it with the
          rest of the necessary information;
      
        - get rid of the constant thresholds in the HPT37x PCI clock detection code,
          switch  to calculating  PCI clock frequency based on the chip's base DPLL
          frequency;
      
        - switch to using the DPLL clock and enable UltraATA/133 mode by default on
          anything newer than HPT370/A;
      
        - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
          unify the HPT36x/37x setup code and the speedproc handlers by joining the
          register setting lists into the table indexed by the clock selected;
      
        - add enablebits for all the chips to avoid touching disabled channels
          (though the HighPoint BIOS seem to only disable the primary one on
          HPT371/N);
      
        - separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
          when setting an UltraDMA mode in hpt37x_tune_chipset().
      
      This version has been tested on HPT370/302/371N.
      
      Thanks to Alan for the inspiration. Hopefully, his libata driver will also
      benefit from the work done on this "obsolete" driver...
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      7b73ee05
    • Sergei Shtylyov's avatar
      hpt366: clean up DMA timeout handling for HPT370 · 4bf63de2
      Sergei Shtylyov authored
      Clean up DMA timeout handling for HPT370:
      
      - hpt370_lostirq_timeout() cleared the DMA status which made __ide_dma_end()
         called afterwards return the incorrect result, and the DMA engine was reset
         both before and after stopping DMA while the HighPoint drivers only do it
         after (which seems logical) -- fix this and also rename the function;
      
      - get rid of the needless mutual recursion in hpt370_ide_dma_end() and
         hpt370_ide_dma_timeout();
      
      - get rid of hpt370_lostirq_timeout() since hwif->ide_dma_end() called from
         the driver's interrupt handler later does all its work.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      4bf63de2
    • Sergei Shtylyov's avatar
      hpt366: merge HPT37x speedproc handlers · 26ccb802
      Sergei Shtylyov authored
      Continue with the driver rewrite:
      
      - move the interrupt twiddling code from the speedproc handlers into the
          init_hwif_hpt366 which allows to merge the two HPT37x speedproc handlers
          into one;
      
      - get rid of in init_hpt366 which solely consists of the duplicate code, then
          fold init_hpt37x() into init_chipset_hpt366();
      
      - fix hpt3xx_tune_drive() to always set the PIO mode requested, not the best
          possible one, change hpt366_config_drive_xfer_rate() accordingly, simplify
          it a bit;
      
      - group all the DMA related code together init_hwif_hpt366(), and generally
          clean up and beautify it.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      26ccb802
    • Sergei Shtylyov's avatar
      hpt366: cache channel's MCR address · abc4ad4c
      Sergei Shtylyov authored
      Begin the real driver redesign. For the starters:
      
      - cache the offset of the IDE channel's MISC. control registers which are used
         throughout the driver in hwif->select_data;
      
      - only touch the relevant MCR when detecting the cable type on HPT374's
         function 1;
      
      - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
         PIO timing register mask for HPT37x.
      
      - rename all the HPT3xx register related variables consistently; clean up the
         whitespace.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      abc4ad4c
    • Sergei Shtylyov's avatar
      hpt366: switch to using pci_get_slot · b4586715
      Sergei Shtylyov authored
      Switch to using pci_get_slot() to get to the function 1 of HPT36x/374 chips --
      there's no need for the driver itself to walk the list of the PCI devices, and
      it also forgets to check the bus number of the device found.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      b4586715
    • Sergei Shtylyov's avatar
      hpt366: print the real chip name at startup · 90778574
      Sergei Shtylyov authored
      - Rework the driver setup code so that it prefixes the driver startup
        messages with the real chip name.
      
      - Print the measured f_CNT value and the DPLL setting for non-HPT3xx
        chips as well.
      
      - Claim the extra 240 bytes of I/O space for all chips, not only for
        those having PCI device ID of 0x0004.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      90778574
    • Andrew Morton's avatar
      hpt366: rework rate filtering tidy · f36702b4
      Andrew Morton authored
      Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      f36702b4
    • Sergei Shtylyov's avatar
      hpt366: rework rate filtering · e139b0b0
      Sergei Shtylyov authored
      - Rework hpt3xx_ratemask() and hpt3xx_ratefilter() so that the former
        returns the max.  mode computed at the load time and doesn't have to do
        bad Ultra33 drive list lookups anymore; remove the duplicate code from
        the latter function.  Move the quirky drive list lookup into
        hpt3xx_quirkproc() where it should have been from the start...
      
      - Disable UltraATA/100 for HPT370 by default as the 33 MHz ATA clock
        being used does not allow for it, and this *greatly* increases the
        transfer speed.
      
      - Save some space by using byte-wide fields in struct hpt_info; switch to
        reading the 8-bit PCI revision ID reg.  only, not the whole 32-bit reg.
      
      - Start incrementing the driver version number with each patch (should
        have been done from the first one posted).
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      e139b0b0
  3. 27 Jan, 2007 1 commit
  4. 13 Dec, 2006 7 commits
    • Sergei Shtylyov's avatar
      [PATCH] HPT37x: read f_CNT saved by BIOS from port · f13c1526
      Sergei Shtylyov authored
      The undocumented register BIOS uses for saving f_CNT seems to only be
      mapped to I/O space while all the other HPT3xx regs are dual-mapped.  Looks
      like another HighPoint's dirty trick.  With this patch, the deadly kernel
      oops on the cards having the modern HighPoint BIOSes is now at last gone!
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      f13c1526
    • Sergei Shtylyov's avatar
      [PATCH] ide: HPT3xx: fix PCI clock detection · 26c068da
      Sergei Shtylyov authored
      Use the f_CNT value saved by the HighPoint BIOS if available as reading it
      directly would give us a wrong PCI frequency after DPLL has already been
      calibrated by BIOS.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      26c068da
    • Sergei Shtylyov's avatar
      [PATCH] ide: fix the case of multiple HPT3xx chips present · 73d1dd93
      Sergei Shtylyov authored
      init_chipset_hpt366() modifies some fields of the ide_pci_device_t structure
      depending on the chip's revision, so pass it a copy of the structure to avoid
      issues when multiple different chips are present.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      73d1dd93
    • Sergei Shtylyov's avatar
      [PATCH] ide: fix HPT3xx hotswap support · 33b18a60
      Sergei Shtylyov authored
      Fix the broken hotswap code: on HPT37x it caused RESET- to glitch when
      tristating the bus (the MISC control 3/6 and soft control 2 need to be written
      to in the certain order), and for HPT36x the obsolete HDIO_TRISTATE_HWIF
      ioctl() handler was called instead which treated the state argument wrong.
      Also, get rid of the soft control reg.  1 wtite to enable IDE interrupt --
      this is done in init_hpt37x() already...
      
      Have been tested on HPT370 and 371N.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      33b18a60
    • Sergei Shtylyov's avatar
      [PATCH] ide: optimize HPT37x timing tables · 471a0bda
      Sergei Shtylyov authored
      Save some space on the timing tables by introducing the separate transfer mode
      table in which the mode lookup is done to get the index into the timing table
      itself.  Get rid of the rest of the obsolete/duplicate tables and use one set
      of tables for the whole HPT37x chip family like the HighPoint open-source
      drivers do.  Documnent the different timing register layout for the HPT36x
      chip family (this is my guesswork based on the timing values).
      
      Have been tested and works fine on HPT370/302/371N.
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      471a0bda
    • Sergei Shtylyov's avatar
      [PATCH] ide: fix HPT37x timing tables · 9448732f
      Sergei Shtylyov authored
      Fix/remove bad/unused timing tables: HPT370/A 66 MHz tables weren't really
      needed (the chips are not UltraATA/133 capable and shouldn't support 66 MHz
      PCI) and had many modes over- and underclocked, HPT372 33 MHz table was in
      fact for 66 MHz and 50 MHz table missed UltraDMA mode 6, HPT374 33 MHz table
      was really for 50 MHz...  (Actually, HPT370/A 33 MHz tables also have issues.
      e.g.  HPT370 has PIO modes 0/1 overlocked.)
      
      There's also no need in the separate HPT374 tables because HPT372 timings
      should be the same (and those tables has UltraDMA mode 6 which HPT374 supports
      depending on HPT374_ALLOW_ATA133_6 #define)...
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      9448732f
    • Sergei Shtylyov's avatar
      [PATCH] ide: HPT3xxN clocking fixes · 836c0063
      Sergei Shtylyov authored
      Fix serious problems with the HPT372N clock turnaround code:
      
      - the wrong ports were written to when called for the secondary channel;
      
      - it didn't serialize access to the channels;
      
      - turnaround shou;dn't be done on 66 MHz PCI;
      
      - caching the clock mode per-channel caused it to get out of sync with the
        actual register value.
      
      Additionally, avoid calibrating PLL twice (for each channel) as the second try
      results in a wrong PCI frequency and thus in the wrong timings.
      
      Make the driver deal with HPT302N and HPT371N correctly -- the clocking and
      (seemingly) a need for clock tunaround is the same as for HPT372N.  HPT371/N
      chips have only one, secondary channel, so avoid touching their "pure virtual"
      primary channel, and disable it if the BIOS haven't done this already.
      
      Also, while at it, disable UltraATA/133 for HPT372 by default -- 50 MHz DPLL
      clock don't allow for this speed anyway.  And remove the traces of the former
      bad patch that wasn't even applicable to this version of driver.
      
      Has been tested on HPT370/371N, unfortunately I don't have an instant access
      to the other chips...
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      836c0063
  5. 30 Jun, 2006 1 commit
  6. 03 Feb, 2006 1 commit
  7. 07 Nov, 2005 1 commit
  8. 11 Sep, 2005 1 commit
  9. 27 Jun, 2005 1 commit
  10. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4