1. 27 Jul, 2010 1 commit
    • Russell King's avatar
      ARM: Factor out common code from cpu_proc_fin() · 9ca03a21
      Russell King authored
      
      
      All implementations of cpu_proc_fin() start by disabling interrupts
      and then flush caches.  Rather than have every processors proc_fin()
      implementation do this, move it out into generic code - and move the
      cache flush past setup_mm_for_reboot() (so it can benefit from having
      caches still enabled.)
      
      This allows cpu_proc_fin() to become independent of the L1/L2 cache
      types, and eventually move the L2 cache flushing into the L2 support
      code.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      9ca03a21
  2. 15 Feb, 2010 2 commits
  3. 14 Dec, 2009 1 commit
  4. 02 Oct, 2009 1 commit
  5. 01 Oct, 2008 2 commits
  6. 24 Apr, 2008 1 commit
  7. 18 Apr, 2008 1 commit
  8. 13 Dec, 2006 1 commit
    • Russell King's avatar
      [ARM] Unuse another Linux PTE bit · ad1ae2fe
      Russell King authored
      
      
      L_PTE_ASID is not really required to be stored in every PTE, since we
      can identify it via the address passed to set_pte_at().  So, create
      set_pte_ext() which takes the address of the PTE to set, the Linux
      PTE value, and the additional CPU PTE bits which aren't encoded in
      the Linux PTE value.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ad1ae2fe
  9. 30 Nov, 2006 1 commit
  10. 03 Jul, 2006 1 commit
  11. 30 Jun, 2006 1 commit
  12. 29 Jun, 2006 2 commits
    • Russell King's avatar
      [ARM] Set bit 4 on section mappings correctly depending on CPU · 8799ee9f
      Russell King authored
      
      
      On some CPUs, bit 4 of section mappings means "update the
      cache when written to".  On others, this bit is required to
      be one, and others it's required to be zero.  Finally, on
      ARMv6 and above, setting it turns on "no execute" and prevents
      speculative prefetches.
      
      With all these combinations, no one value fits all CPUs, so we
      have to pick a value depending on the CPU type, and the area
      we're mapping.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      8799ee9f
    • Russell King's avatar
      [ARM] nommu: provide a way for correct control register value selection · 22b19086
      Russell King authored
      
      
      Most MMU-based CPUs have a restriction on the setting of the data cache
      enable and mmu enable bits in the control register, whereby if the data
      cache is enabled, the MMU must also be enabled.  Enabling the data
      cache without the MMU is an invalid combination.
      
      However, there are CPUs where the data cache can be enabled without the
      MMU.
      
      In order to allow these CPUs to take advantage of that, provide a
      method whereby each proc-*.S file defines the control regsiter value
      for use with nommu (with the MMU disabled.)  Later on, when we add
      support for enabling the MMU on these devices, we can adjust the
      "crval" macro to also enable the data cache for nommu.
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      22b19086
  13. 28 Jun, 2006 1 commit
  14. 21 Mar, 2006 2 commits
  15. 20 Sep, 2005 1 commit
  16. 09 Sep, 2005 1 commit
  17. 30 Jun, 2005 2 commits
  18. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4