1. 13 Apr, 2012 1 commit
  2. 15 Feb, 2012 1 commit
  3. 23 Jan, 2012 1 commit
    • Will Deacon's avatar
      ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs · a092f2b1
      Will Deacon authored
      
      
      To ensure correct alignment of cacheline-aligned data, the maximum
      cacheline size needs to be known at compile time.
      
      Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely
      that there will be future ARMv7 implementations with the same line size)
      then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline
      size. For CPUs with smaller caches, this will result in some harmless
      padding but will help with single zImage work and avoid hitting subtle
      bugs with misaligned data structures.
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      a092f2b1
  4. 19 Dec, 2011 1 commit
  5. 08 Dec, 2011 1 commit
  6. 31 Oct, 2011 3 commits
  7. 08 Jul, 2011 1 commit
  8. 07 Jul, 2011 1 commit
    • Anton Vorontsov's avatar
      ARM: cns3xxx: Add support for L2 Cache Controller · 93e85d8e
      Anton Vorontsov authored
      
      
      CNS3xxx SOCs have L310-compatible cache controller, so let's use it.
      
      With this patch benchmarking with 'gzip' shows that performance is
      doubled, and I'm still able to boot full-fledged userland over NFS
      (using PCIe NIC), so the support should be pretty robust.
      
      p.s. While CNS3xxx reports that it has PL310, it still needs to wait
      on cache line operations, so we should not select 'CACHE_PL310',
      which is a micro-optimization that removes these waits for v7 CPUs.
      Someday we'd better rename CACHE_PL310 Kconfig option into
      NO_CACHE_WAIT or something less ambiguous.
      Signed-off-by: default avatarAnton Vorontsov <avorontsov@mvista.com>
      93e85d8e
  9. 20 Jun, 2011 1 commit
    • John Linn's avatar
      ARM: Xilinx: Adding Xilinx board support · b85a3ef4
      John Linn authored
      
      
      The 1st board support is minimal to get a system up and running
      on the Xilinx platform.
      
      This platform reuses the clock implementation from plat-versatile, and
      it depends entirely on CONFIG_OF support.  There is only one board
      support file which obtains all device information from a device tree
      dtb file which is passed to the kernel at boot time.
      Signed-off-by: default avatarJohn Linn <john.linn@xilinx.com>
      b85a3ef4
  10. 07 Mar, 2011 1 commit
  11. 23 Feb, 2011 1 commit
  12. 21 Feb, 2011 1 commit
  13. 10 Feb, 2011 1 commit
  14. 09 Feb, 2011 1 commit
    • Russell King's avatar
      ARM: Avoid building unsafe kernels on OMAP2 and MX3 · 15490ef8
      Russell King authored
      
      
      OMAP2 (armv6) and MX3 turn off support for the V6K instructions, which
      when they include support for SMP kernels means that the resulting
      kernel is unsafe on SMP and can result in corrupted filesystems as we
      end up using unsafe bitops.
      
      Re-enable the use of V6K instructions on such kernels, and let such
      kernels running on V6 CPUs eat undefined instruction faults which will
      be much safer than filesystem corruption.  Next merge window we can fix
      this properly (as it requires a much bigger set of changes.)
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      15490ef8
  15. 02 Feb, 2011 6 commits
  16. 06 Jan, 2011 1 commit
  17. 18 Dec, 2010 2 commits
  18. 17 Nov, 2010 1 commit
    • Magnus Damm's avatar
      ARM: mach-shmobile: Initial AG5 and AG5EVM support · 6d9598e2
      Magnus Damm authored
      
      
      This patch adds initial support for Renesas SH-Mobile AG5.
      
      At this point the AG5 CPU support is limited to the ARM
      core, SCIF serial and a CMT timer together with L2 cache
      and the GIC. The AG5EVM board also supports Ethernet.
      
      Future patches will add support for GPIO, INTCS, CPGA
      and platform data / driver updates for devices such as
      IIC, LCDC, FSI, KEYSC, CEU and SDHI among others.
      
      The code in entry-macro.S will be cleaned up when the
      ARM IRQ demux code improvements have been merged.
      
      Depends on the AG5EVM mach-type recently registered but
      not yet present in arch/arm/tools/mach-types.
      
      As the AG5EVM board comes with 512MiB memory it is
      recommended to turn on HIGHMEM.
      
      Many thanks to Yoshii-san for initial bring up.
      Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      6d9598e2
  19. 04 Nov, 2010 2 commits
    • Leif Lindholm's avatar
      ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processors · 64d2dc38
      Leif Lindholm authored
      
      
      The SWP instruction was deprecated in the ARMv6 architecture,
      superseded by the LDREX/STREX family of instructions for
      load-linked/store-conditional operations. The ARMv7 multiprocessing
      extensions mandate that SWP/SWPB instructions are treated as undefined
      from reset, with the ability to enable them through the System Control
      Register SW bit.
      
      This patch adds the alternative solution to emulate the SWP and SWPB
      instructions using LDREX/STREX sequences, and log statistics to
      /proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also
      modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when
      user RO.
      Signed-off-by: default avatarLeif Lindholm <leif.lindholm@arm.com>
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarKirill A. Shutemov <kirill@shutemov.name>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      64d2dc38
    • Catalin Marinas's avatar
      ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUs · 247055aa
      Catalin Marinas authored
      
      
      This patch removes the domain switching functionality via the set_fs and
      __switch_to functions on cores that have a TLS register.
      
      Currently, the ioremap and vmalloc areas share the same level 1 page
      tables and therefore have the same domain (DOMAIN_KERNEL). When the
      kernel domain is modified from Client to Manager (via the __set_fs or in
      the __switch_to function), the XN (eXecute Never) bit is overridden and
      newer CPUs can speculatively prefetch the ioremap'ed memory.
      
      Linux performs the kernel domain switching to allow user-specific
      functions (copy_to/from_user, get/put_user etc.) to access kernel
      memory. In order for these functions to work with the kernel domain set
      to Client, the patch modifies the LDRT/STRT and related instructions to
      the LDR/STR ones.
      
      The user pages access rights are also modified for kernel read-only
      access rather than read/write so that the copy-on-write mechanism still
      works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register
      (CPU_32v6K is defined) since writing the TLS value to the high vectors page
      isn't possible.
      
      The user addresses passed to the kernel are checked by the access_ok()
      function so that they do not point to the kernel space.
      Tested-by: default avatarAnton Vorontsov <cbouatmailru@gmail.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      247055aa
  20. 26 Oct, 2010 1 commit
  21. 02 Sep, 2010 1 commit
  22. 05 Aug, 2010 2 commits
  23. 09 Jul, 2010 1 commit
  24. 02 Jul, 2010 1 commit
  25. 01 Jul, 2010 1 commit
  26. 17 May, 2010 1 commit
  27. 11 May, 2010 1 commit
  28. 03 May, 2010 1 commit
  29. 02 May, 2010 1 commit
  30. 14 Apr, 2010 1 commit