1. 09 Oct, 2012 2 commits
  2. 06 Sep, 2012 1 commit
  3. 18 Jul, 2012 5 commits
  4. 11 Jul, 2012 1 commit
    • Chris Metcalf's avatar
      arch/tile: introduce GXIO IORPC framework for tilegx · 37b82b5d
      Chris Metcalf authored
      The GXIO I/O RPC subsystem handles exporting I/O hardware resources to
      Linux and to applications running under Linux.
      For instance, memory which is made available for I/O DMA must be mapped
      by an I/O TLB; that means that such memory must be locked down by Linux,
      so that it is not swapped or otherwise reused, as long as those I/O
      TLB entries are active. Similarly, configuring direct hardware access
      introduces new validation requirements. If a user application registers
      memory, Linux must ensure that the supplied virtual addresses are valid,
      and turn them into client physical addresses. Similarly, when Linux then
      supplies those client physical addresses to the Tilera hypervisor, it
      must in turn validate those before turning them into the real physical
      addresses which are required by the hardware.
      To the extent that these sorts of activities were required on previous
      TILE architecture processors, they were implemented in a device-specific
      fashion. This meant that every I/O device had its own Tilera hypervisor
      driver, its own Linux driver, and in some cases its own user-level
      library support. There was a large amount of more-or-less functionally
      identical code in different places, particularly in the different Linux
      drivers. For TILE-Gx, this support has been generalized into a common
      framework, known as the I/O RPC framework or just IORPC.
      The two "gxio" directories (one for headers, one for sources) start
      with just a few files in each with this infrastructure commit, but
      after adding support for the on-board I/O shims for networking, PCI,
      USB, crypto, compression, I2CS, etc., there end up being about 20 files
      in each directory.
      More information on the IORPC framework is in the <hv/iorpc.h> header,
      included in this commit.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
  5. 25 May, 2012 3 commits
    • Chris Metcalf's avatar
      arch/tile: mark TILEGX as not EXPERIMENTAL · acd1a19e
      Chris Metcalf authored
      Also create a TILEPRO config setting to use for #ifdefs where it
      is cleaner to do so, and make the 64BIT setting depend directly
      on the setting of TILEGX.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
    • Chris Metcalf's avatar
      arch/tile: support multiple huge page sizes dynamically · 621b1955
      Chris Metcalf authored
      This change adds support for a new "super" bit in the PTE, using the new
      arch_make_huge_pte() method.  The Tilera hypervisor sees the bit set at a
      given level of the page table and gangs together 4, 16, or 64 consecutive
      pages from that level of the hierarchy to create a larger TLB entry.
      One extra "super" page size can be specified at each of the three levels
      of the page table hierarchy on tilegx, using the "hugepagesz" argument
      on the boot command line.  A new hypervisor API is added to allow Linux
      to tell the hypervisor how many PTEs to gang together at each level of
      the page table.
      To allow pre-allocating huge pages larger than the buddy allocator can
      handle, this change modifies the Tilera bootmem support to put all of
      memory on tilegx platforms into bootmem.
      As part of this change I eliminate the vestigial CONFIG_HIGHPTE support,
      which never worked anyway, and eliminate the hv_page_size() API in favor
      of the standard vma_kernel_pagesize() API.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
    • Chris Metcalf's avatar
      arch/tile: Allow tilegx to build with either 16K or 64K page size · d5d14ed6
      Chris Metcalf authored
      This change introduces new flags for the hv_install_context()
      API that passes a page table pointer to the hypervisor.  Clients
      can explicitly request 4K, 16K, or 64K small pages when they
      install a new context.  In practice, the page size is fixed at
      kernel compile time and the same size is always requested every
      time a new page table is installed.
      The <hv/hypervisor.h> header changes so that it provides more abstract
      macros for managing "page" things like PFNs and page tables.  For
      example there is now a HV_DEFAULT_PAGE_SIZE_SMALL instead of the old
      HV_PAGE_SIZE_SMALL.  The various PFN routines have been eliminated and
      only PA- or PTFN-based ones remain (since PTFNs are always expressed
      in fixed 2KB "page" size).  The page-table management macros are
      renamed with a leading underscore and take page-size arguments with
      the presumption that clients will use those macros in some single
      place to provide the "real" macros they will use themselves.
      I happened to notice the old hv_set_caching() API was totally broken
      (it assumed 4KB pages) so I changed it so it would nominally work
      correctly with other page sizes.
      Tag modules with the page size so you can't load a module built with
      a conflicting page size.  (And add a test for SMP while we're at it.)
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
  6. 21 May, 2012 2 commits
  7. 18 May, 2012 1 commit
    • Chris Metcalf's avatar
      tilegx: enable SYSCALL_WRAPPERS support · e6d9668e
      Chris Metcalf authored
      Some discussion with the glibc mailing lists revealed that this was
      necessary for 64-bit platforms with MIPS-like sign-extension rules
      for 32-bit values.  The original symptom was that passing (uid_t)-1 to
      setreuid() was failing in programs linked -pthread because of the "setxid"
      mechanism for passing setxid-type function arguments to the syscall code.
      SYSCALL_WRAPPERS handles ensuring that all syscall arguments end up with
      proper sign-extension and is thus the appropriate fix for this problem.
      On other platforms (s390, powerpc, sparc64, and mips) this was fixed
      in  The general issue is tracked as CVE-2009-0029.
      Cc: <stable@vger.kernel.org>
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
  8. 05 May, 2012 2 commits
  9. 02 Apr, 2012 3 commits
  10. 04 Dec, 2011 1 commit
  11. 04 Oct, 2011 1 commit
    • John Stultz's avatar
      time: Cleanup old CONFIG_GENERIC_TIME references that snuck in · dcb69290
      John Stultz authored
      Awhile back I removed all the CONFIG_GENERIC_TIME referecnes as
      the last of the non-GENERIC_TIME arches were converted.
      However, due to the functionality being important and around for
      awhile, there apparently were some out of tree hardware enablement
      patches that used it and have since been merged.
      This patch removes the remaining instances of GENERIC_TIME.
      Singed-off-by: default avatarJohn Stultz <john.stultz@linaro.org>
  12. 03 Aug, 2011 1 commit
  13. 27 May, 2011 1 commit
    • Chris Metcalf's avatar
      arch/tile: more /proc and /sys file support · f133ecca
      Chris Metcalf authored
      This change introduces a few of the less controversial /proc and
      /proc/sys interfaces for tile, along with sysfs attributes for
      various things that were originally proposed as /proc/tile files.
      It also adjusts the "hardwall" proc API.
      Arnd Bergmann reviewed the initial arch/tile submission, which
      included a complete set of all the /proc/tile and /proc/sys/tile
      knobs that we had added in a somewhat ad hoc way during initial
      development, and provided feedback on where most of them should go.
      One knob turned out to be similar enough to the existing
      /proc/sys/debug/exception-trace that it was re-implemented to use
      that model instead.
      Another knob was /proc/tile/grid, which reported the "grid" dimensions
      of a tile chip (e.g. 8x8 processors = 64-core chip).  Arnd suggested
      looking at sysfs for that, so this change moves that information
      to a pair of sysfs attributes (chip_width and chip_height) in the
      /sys/devices/system/cpu directory.  We also put the "chip_serial"
      and "chip_revision" information from our old /proc/tile/board file
      as attributes in /sys/devices/system/cpu.
      Other information collected via hypervisor APIs is now placed in
      /sys/hypervisor.  We create a /sys/hypervisor/type file (holding the
      constant string "tilera") to be parallel with the Xen use of
      /sys/hypervisor/type holding "xen".  We create three top-level files,
      "version" (the hypervisor's own version), "config_version" (the
      version of the configuration file), and "hvconfig" (the contents of
      the configuration file).  The remaining information from our old
      /proc/tile/board and /proc/tile/switch files becomes an attribute
      group appearing under /sys/hypervisor/board/.
      Finally, after some feedback from Arnd Bergmann for the previous
      version of this patch, the /proc/tile/hardwall file is split up into
      two conceptual parts.  First, a directory /proc/tile/hardwall/ which
      contains one file per active hardwall, each file named after the
      hardwall's ID and holding a cpulist that says which cpus are enclosed by
      the hardwall.  Second, a /proc/PID file "hardwall" that is either
      empty (for non-hardwall-using processes) or contains the hardwall ID.
      Finally, this change pushes the /proc/sys/tile/unaligned_fixup/
      directory, with knobs controlling the kernel code for handling the
      fixup of unaligned exceptions.
      Reviewed-by: default avatarArnd Bergmann <arnd@arndb.de>
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
  14. 26 May, 2011 1 commit
  15. 04 May, 2011 1 commit
  16. 31 Mar, 2011 1 commit
  17. 30 Mar, 2011 1 commit
  18. 25 Mar, 2011 1 commit
  19. 10 Mar, 2011 3 commits
    • Chris Metcalf's avatar
      arch/tile: support 4KB page size as well as 64KB · 76c567fb
      Chris Metcalf authored
      The Tilera architecture traditionally supports 64KB page sizes
      to improve TLB utilization and improve performance when the
      hardware is being used primarily to run a single application.
      For more generic server scenarios, it can be beneficial to run
      with 4KB page sizes, so this commit allows that to be specified
      (by modifying the arch/tile/include/hv/pagesize.h header).
      As part of this change, we also re-worked the PTE management
      slightly so that PTE writes all go through a __set_pte() function
      where we can do some additional validation.  The set_pte_order()
      function was eliminated since the "order" argument wasn't being used.
      One bug uncovered was in the PCI DMA code, which wasn't properly
      flushing the specified range.  This was benign with 64KB pages,
      but with 4KB pages we were getting some larger flushes wrong.
      The per-cpu memory reservation code also needed updating to
      conform with the newer percpu stuff; before it always chose 64KB,
      and that was always correct, but with 4KB granularity we now have
      to pay closer attention and reserve the amount of memory that will
      be requested when the percpu code starts allocating.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
    • Chris Metcalf's avatar
      arch/tile: add some more VMSPLIT options and use consistent naming · 09c17eab
      Chris Metcalf authored
      This renames 3G_OPT to 2_75G, and adds 2_5G and 2_25G.
      For memory-intensive applications that are also network-buffer
      intensive it can be helpful to be able to tune the virtual address
      of the start of kernel memory.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
    • Chris Metcalf's avatar
      arch/tile: fix some comments and whitespace · 5fb682b0
      Chris Metcalf authored
      This is a grab bag of changes with no actual change to generated code.
      This includes whitespace and comment typos, plus a couple of stale
      comments being removed.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
  20. 23 Feb, 2011 1 commit
  21. 21 Jan, 2011 2 commits
  22. 20 Jan, 2011 1 commit
    • David Rientjes's avatar
      kconfig: rename CONFIG_EMBEDDED to CONFIG_EXPERT · 6a108a14
      David Rientjes authored
      The meaning of CONFIG_EMBEDDED has long since been obsoleted; the option
      is used to configure any non-standard kernel with a much larger scope than
      only small devices.
      This patch renames the option to CONFIG_EXPERT in init/Kconfig and fixes
      references to the option throughout the kernel.  A new CONFIG_EMBEDDED
      option is added that automatically selects CONFIG_EXPERT when enabled and
      can be used in the future to isolate options that should only be
      considered for embedded systems (RISC architectures, SLOB, etc).
      Calling the option "EXPERT" more accurately represents its intention: only
      expert users who understand the impact of the configuration changes they
      are making should enable it.
      Reviewed-by: default avatarIngo Molnar <mingo@elte.hu>
      Acked-by: default avatarDavid Woodhouse <david.woodhouse@intel.com>
      Signed-off-by: default avatarDavid Rientjes <rientjes@google.com>
      Cc: Greg KH <gregkh@suse.de>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Jens Axboe <axboe@kernel.dk>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Robin Holt <holt@sgi.com>
      Cc: <linux-arch@vger.kernel.org>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
  23. 24 Nov, 2010 1 commit
    • Chris Metcalf's avatar
      pci root complex: support for tile architecture · f02cbbe6
      Chris Metcalf authored
      This change enables PCI root complex support for TILEPro.  Unlike
      TILE-Gx, TILEPro has no support for memory-mapped I/O, so the PCI
      support consists of hypervisor upcalls for PIO, DMA, etc.  However,
      the performance is fine for the devices we have tested with so far
      (1Gb Ethernet, SATA, etc.).
      The <asm/io.h> header was tweaked to be a little bit more aggressive
      about disabling attempts to map/unmap IO port space.  The hacky
      <asm/pci-bridge.h> header was rolled into the <asm/pci.h> header
      and the result was simplified.  Both of the latter two headers were
      preliminary versions not meant for release before now - oh well.
      There is one quirk for our TILEmpower platform, which accidentally
      negotiates up to 5GT and needs to be kicked down to 2.5GT.
      Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
  24. 28 Oct, 2010 1 commit
  25. 27 Oct, 2010 1 commit
  26. 15 Oct, 2010 1 commit