1. 26 Apr, 2011 3 commits
    • Rajkumar Manoharan's avatar
      ath9k: set beacon related ps flags on bss_info change · 92c6f76c
      Rajkumar Manoharan authored
      
      
      Requesting beacon sync up to configure beacon timers properly
      in hw, has be done after doing beacon config with default values.
      Setting the flags in beacon config is causing the device to not
      enter into network sleep on idle state.
      Signed-off-by: default avatarRajkumar Manoharan <rmanoharan@atheros.com>
      Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
      92c6f76c
    • Rajkumar Manoharan's avatar
      ath9k_hw: Fix Tx IQ Calibration hang issue in AR9003 chips · 3782c69d
      Rajkumar Manoharan authored
      
      
      On AR9003 chips, doing three IQ calibrations will possibly cause chip
      in stuck state. In noisy environment, chip could receive
      a packet during the middle of three calibrations and it causes
      the conflict of HW access and the eventual failure. It also
      causes IQ calibration outliers which results in poor Tx EVM.
      
      The IQ Cal procedure is after resetting the chip, run IQ cal 3 times
      per each cal cycle and find the two closest readings and average of two.
      The advantage of running Tx IQ cal more than once is that we can compare
      calibration results for the same gain setting over multiple iterations.
      Most of the cases the IQ failures were observed after first pass.
      
      For the AR9485 and later chips, Tx IQ Calibration is performed along
      with AGC cal. But for pre-AR9485 chips, Tx IQ cal HW has to be separated
      from the rest of calibration HW to avoid chip hang. After all
      calibrations are done in HW, we can start SW post-processing.
      By doing this way, we minimize the SW difference among all chips.
      
      The order of calibration (run IQ cal before other calibration) is also
      needed to avoid chip hang for chips before AR9485. This issue was
      originally observed with AR9382.
      
      During the issue kernel log was filled with following message
      ath: timeout (100000 us) on reg 0xa640: 0x00000001 & 0x00000001 != 0x00000000
      ath: timeout (100000 us) on reg 0xa2c4: 0x00158dd9 & 0x00000001 != 0x00000000
      ath: Unable to reset channel (2412 MHz), reset status -5
      ath: Unable to set channel
      Signed-off-by: default avatarRajkumar Manoharan <rmanoharan@atheros.com>
      Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
      3782c69d
    • John W. Linville's avatar
  2. 25 Apr, 2011 37 commits