1. 23 Feb, 2015 1 commit
  2. 25 Jul, 2014 1 commit
  3. 05 May, 2014 2 commits
  4. 08 Mar, 2014 1 commit
    • David Ertman's avatar
      e1000e: Fix SHRA register access for 82579 · 96dee024
      David Ertman authored
      Previous commit c3a0dce3
      
       fixed an overrun for the RAR on i218 devices.
      This commit also attempted to homogenize the RAR/SHRA access for all parts
      accessed by the e1000e driver.  This change introduced an error for
      assigning MAC addresses to guest OS's for 82579 devices.
      
      Only RAR[0] is accessible to the driver for 82579 parts, and additional
      addresses must be placed into the SHRA[L|H] registers.  The rar_entry_count
      was changed in the previous commit to an inaccurate value that accounted
      for all RAR and SHRA registers, not just the ones usable by the driver.
      
      This patch fixes the count to the correct value and adjusts the
      e1000_rar_set_pch2lan() function to user the correct index.
      
      Cc: John Greene <jogreene@redhat.com>
      Signed-off-by: default avatarDave Ertman <davidx.m.ertman@intel.com>
      Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      96dee024
  5. 07 Mar, 2014 3 commits
  6. 13 Sep, 2013 1 commit
    • David Ertman's avatar
      e1000e: fix overrun of PHY RAR array · c3a0dce3
      David Ertman authored
      
      
      When copying the MAC RAR registers to PHY there is an error in the
      calculation of the rar_entry_count, which causes a write of unknown/
      undefined register space in the MAC to unknown/undefined register space in
      the PHY.
      
      This patch fixes the overrun with writing to the PHY RAR and also fixes the
      ethtool offline register tests so that the correctly addressed registers
      have the appropriate bitmasks for R/W and RO bits for affected parts.
      
      Shawn Rader gets credit for finding and fixing the register overrun.
      Signed-off-by: default avatarDave Ertman <davidx.m.ertman@intel.com>
      CC: Shawn Rader <shawn.t.rader@intel.com>
      Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      c3a0dce3
  7. 28 Jul, 2013 1 commit
  8. 28 Mar, 2013 3 commits
  9. 05 Mar, 2013 1 commit
    • Bruce Allan's avatar
      e1000e: workaround DMA unit hang on I218 · e08f626b
      Bruce Allan authored
      
      
      At 1000Mbps link speed, one of the MAC's internal clocks can be stopped for
      up to 4us when entering K1 (a power mode of the MAC-PHY interconnect).  If
      the MAC is waiting for completion indications for 2 DMA write requests into
      Host memory (e.g. descriptor writeback or Rx packet writing) and the
      indications occur while the clock is stopped, both indications will be
      missed by the MAC causing the MAC to wait for the completion indications
      and be unable to generate further DMA write requests.  This results in an
      apparent hardware hang.
      
      Work-around the issue by disabling the de-assertion of the clock request
      when 1000Mbps link is acquired (K1 must be disabled while doing this).
      Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
      Tested-by: default avatarJeff Pieper <jeffrey.e.pieper@intel.com>
      Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
      e08f626b
  10. 05 Feb, 2013 1 commit