1. 14 Jun, 2009 3 commits
    • Jerome Glisse's avatar
      drm/radeon: introduce kernel modesetting for radeon hardware · 771fe6b9
      Jerome Glisse authored
      Add kernel modesetting support to radeon driver, use the ttm memory
      manager to manage memory and DRM/GEM to provide userspace API.
      In order to avoid backward compatibility issue and to allow clean
      design and code the radeon kernel modesetting use different code path
      than old radeon/drm driver.
      When kernel modesetting is enabled the IOCTL of radeon/drm
      driver are considered as invalid and an error message is printed
      in the log and they return failure.
      KMS enabled userspace will use new API to talk with the radeon/drm
      driver. The new API provide functions to create/destroy/share/mmap
      buffer object which are then managed by the kernel memory manager
      (here TTM). In order to submit command to the GPU the userspace
      provide a buffer holding the command stream, along this buffer
      userspace have to provide a list of buffer object used by the
      command stream. The kernel radeon driver will then place buffer
      in GPU accessible memory and will update command stream to reflect
      the position of the different buffers.
      The kernel will also perform security check on command stream
      provided by the user, we want to catch and forbid any illegal use
      of the GPU such as DMA into random system memory or into memory
      not owned by the process supplying the command stream. This part
      of the code is still incomplete and this why we propose that patch
      as a staging driver addition, future security might forbid current
      experimental userspace to run.
      This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX
      (radeon up to X1950). Works is underway to provide support for R6XX,
      R7XX and newer hardware (radeon from HD2XXX to HD4XXX).
          Jerome Glisse <jglisse@redhat.com>
          Dave Airlie <airlied@redhat.com>
          Alex Deucher <alexdeucher@gmail.com>
      Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
    • Thomas Hellstrom's avatar
      drm: Add the TTM GPU memory manager subsystem. · ba4e7d97
      Thomas Hellstrom authored
      TTM is a GPU memory manager subsystem designed for use with GPU
      devices with various memory types (On-card VRAM, AGP,
      PCI apertures etc.). It's essentially a helper library that assists
      the DRM driver in creating and managing persistent buffer objects.
      TTM manages placement of data and CPU map setup and teardown on
      data movement. It can also optionally manage synchronization of
      data on a per-buffer-object level.
      TTM takes care to provide an always valid virtual user-space address
      to a buffer object which makes user-space sub-allocation of
      big buffer objects feasible.
      TTM uses a fine-grained per buffer-object locking scheme, taking
      care to release all relevant locks when waiting for the GPU.
      Although this implies some locking overhead, it's probably a big
      win for devices with multiple command submission mechanisms, since
      the lock contention will be minimal.
      TTM can be used with whatever user-space interface the driver
      chooses, including GEM. It's used by the upcoming Radeon KMS DRM driver
      and is also the GPU memory management core of various new experimental
      DRM drivers.
      Signed-off-by: default avatarThomas Hellstrom <thellstrom@vmware.com>
      Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
    • Dave Airlie's avatar
      drm/radeon: fix mobility flags on new PCI IDs. · 602c11a8
      Dave Airlie authored
      These aren't used that much on r600, but may be needed in the future,
      so get them correct now.
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  2. 11 Jun, 2009 7 commits
  3. 09 Jun, 2009 1 commit
  4. 19 May, 2009 1 commit
    • Jesse Barnes's avatar
      drm/i915: allocate large pointer arrays with vmalloc · 8e7d2b2c
      Jesse Barnes authored
      For awhile now, many of the GEM code paths have allocated page or
      object arrays with the slab allocator.  This is nice and fast, but
      won't work well if memory is fragmented, since the slab allocator works
      with physically contiguous memory (i.e. order > 2 allocations are
      likely to fail fairly early after booting and doing some work).
      This patch works around the issue by falling back to vmalloc for
      >PAGE_SIZE allocations.  This is ugly, but much less work than chaining
      a bunch of pages together by hand (suprisingly there's not a bunch of
      generic kernel helpers for this yet afaik).  vmalloc space is somewhat
      precious on 32 bit kernels, but our allocations shouldn't be big enough
      to cause problems, though they're routinely more than a page.
      Note that this patch doesn't address the unchecked
      alloc-based-on-ioctl-args in GEM; that needs to be fixed in a separate
      Also, I've deliberately ignored the DRM's "area" junk.  I don't think
      anyone actually uses it anymore and I'm hoping it gets ripped out soon.
      [Updated: removed size arg to new free function.  We could unify the
      free functions as well once the DRM mem tracking is ripped out.]
      fd.o bug #20152 (part 1/3)
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
  5. 14 May, 2009 1 commit
  6. 21 Apr, 2009 1 commit
  7. 13 Apr, 2009 1 commit
  8. 08 Apr, 2009 1 commit
    • Eric Anholt's avatar
      drm/i915: Allow tiling of objects with bit 17 swizzling by the CPU. · 280b713b
      Eric Anholt authored
      Save the bit 17 state of the pages when freeing the page list, and
      reswizzle them if necessary when rebinding the pages (in case they were
      swapped out).  Since we have userland with expectations that the swizzle
      enums let it pread and pwrite contents accurately, we can't expose a new
      swizzle enum for bit 17 (which it would have to GTT map to handle), so we
      handle it down in pread and pwrite by swizzling the copy when bit 17 of the
      page address is set.
      Signed-off-by: default avatarEric Anholt <eric@anholt.net>
  9. 02 Apr, 2009 3 commits
  10. 29 Mar, 2009 4 commits
  11. 27 Mar, 2009 2 commits
  12. 26 Mar, 2009 1 commit
  13. 12 Mar, 2009 10 commits
  14. 10 Mar, 2009 1 commit
  15. 24 Feb, 2009 2 commits
  16. 19 Feb, 2009 1 commit