1. 26 Aug, 2007 1 commit
  2. 23 Aug, 2007 5 commits
  3. 22 Aug, 2007 11 commits
  4. 21 Aug, 2007 5 commits
  5. 20 Aug, 2007 2 commits
  6. 18 Aug, 2007 6 commits
  7. 17 Aug, 2007 6 commits
    • Peter Chubb's avatar
      [IA64] Enable early console for Ski simulator · 471e7a44
      Peter Chubb authored
      When using Ski to debug early startup, it's a bit of a pain not to
      have printk.
      This patch enables the simulated console very early.
      It may be worth conditionalising on the command line... but this is
      enough for now.
      Signed-off-by: default avatarPeter Chubb <peterc@gelato.unsw.edu.au>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
    • Shaohua Li's avatar
      [IA64] forbid ptrace changes psr.ri to 3 · b09e789c
      Shaohua Li authored
      The "ri" field in the processor status register only has defined
      values of 0, 1, 2.  Do not let ptrace set this to 3.  As with
      other reserved fields in registers we silently discard the value.
      Signed-off-by: default avatarShaohua Li <shaohua.li@intel.com>
      Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
    • Kumar Gala's avatar
      [POWERPC] Fix 8xx compile failure · 0af666fa
      Kumar Gala authored
        CC      arch/powerpc/sysdev/commproc.o
      arch/powerpc/sysdev/fsl_soc.c: In function fsl_pcmcia_of_init:
      arch/powerpc/sysdev/fsl_soc.c:1109: error: implicit declaration of function of_platform_device_create
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Becky Bruce's avatar
      [POWERPC] Fix FSL BookE machine check reporting · 86d7a9a9
      Becky Bruce authored
      Reserved MCSR bits on FSL BookE parts may have spurious values
      when mcheck occurs.  Mask these off when printing the MCSR to
      avoid confusion.  Also, get rid of the MCSR_GL_CI bit defined
      for e500 - this bit doesn't actually have any meaning.
      Signed-off-by: default avatarBecky Bruce <becky.bruce@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Kumar Gala's avatar
      [POWERPC] Fix interrupt routing and setup of ULI M1575 on FSL boards · b66510cb
      Kumar Gala authored
      The interrupt routing in the device trees for the ULI M1575 was
      inproperly using the interrupt line field as pci function.  Fixed
      up the device tree's to actual conform for to specification and
      changed the interrupt mapping code so it just uses a static mapping
      setup as follows:
      PIRQA - IRQ9
      PIRQB - IRQ10
      PIRQC - IRQ11
      PIRQD - IRQ12
      USB 1.1 OCHI (1c.0) - IRQ12
      USB 1.1 OCHI (1c.1) - IRQ9
      USB 1.1 OCHI (1c.2) - IRQ10
      USB 1.1 ECHI (1c.3) - IRQ11
      LAN (1b.0) - IRQ6
      AC97 (1d.0) - IRQ6
      Modem (1d.1) - IRQ6
      HD Audio (1d.2) - IRQ6
      SATA (1f.1) - IRQ5
      SMB (1e.1) - IRQ7
      PMU (1e.2) - IRQ7
      PATA (1f.0) - IRQ14/15
      Took the oppurtunity to refactor the code into a single file so we
      don't have to duplicate these fixes on the two current boards in the
      tree and several forth coming boards that will also need the code.
      Fixed RTC support that requires a dummy memory read on the P2P bridge
      to unlock the RTC and setup the default of the RTC alarm registers to
      match with a basic x86 style CMOS RTC.
      Moved code that poked ISA registers to a FIXUP_FINAL quirk to ensure
      the PCI IO space has been setup properly before we start poking ISA
      registers at random locations.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Kumar Gala's avatar
      [POWERPC] Add interrupt resource for RTC CMOS driver · ada3ea6f
      Kumar Gala authored
      The RTC CMOS driver expects the interrupt to be a resource of the platform
      device.  Use a fixed interrupt value of 8 since on PPC if we are using this
      its off an i8259 which we ensure has interrupt numbers 0..15.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  8. 16 Aug, 2007 4 commits