1. 25 Mar, 2009 2 commits
  2. 23 Mar, 2009 1 commit
  3. 19 Mar, 2009 2 commits
  4. 18 Mar, 2009 6 commits
  5. 17 Mar, 2009 6 commits
    • Geoff Levand's avatar
      powerpc/ps3: ps3_defconfig updates · 9aac3975
      Geoff Levand authored
      
      
      Update ps3_defconfig.
      
      Sets these options:
      
        CONFIG_PS3_VRAM=m
        CONFIG_BLK_DEV_DM=m
        CONFIG_USB_HIDDEV=y
        CONFIG_EXT4_FS=y
      Signed-off-by: default avatarGeoff Levand <geoffrey.levand@am.sony.com>
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      9aac3975
    • Masami Hiramatsu's avatar
      prevent boosting kprobes on exception address · 30390880
      Masami Hiramatsu authored
      
      
      Don't boost at the addresses which are listed on exception tables,
      because major page fault will occur on those addresses.  In that case,
      kprobes can not ensure that when instruction buffer can be freed since
      some processes will sleep on the buffer.
      
      kprobes-ia64 already has same check.
      Signed-off-by: default avatarMasami Hiramatsu <mhiramat@redhat.com>
      Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      30390880
    • Kumar Gala's avatar
      powerpc/mm: Respect _PAGE_COHERENT on classic ppc32 SW · a4bd6a93
      Kumar Gala authored
      
      
      Since we now set _PAGE_COHERENT in the Linux PTE we shouldn't be clearing
      it out before we setup the SW TLB.  Today all the SW TLB machines
      (603/e300) that we support are non-SMP, however there are some errata on
      some devices that cause us to set _PAGE_COHERENT via CPU_FTR_NEED_COHERENT.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      a4bd6a93
    • Piotr Ziecik's avatar
      powerpc/5200: Enable CPU_FTR_NEED_COHERENT for MPC52xx · c9310920
      Piotr Ziecik authored
      BestComm, a DMA engine in MPC52xx SoC, requires snooping when
      CPU caches are enabled to work properly.
      
      Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines
      introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup
      code' (sha1: 4c456a67
      
      ).
      Signed-off-by: default avatarPiotr Ziecik <kosmo@semihalf.com>
      Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
      c9310920
    • Linus Torvalds's avatar
      Fast TSC calibration: calculate proper frequency error bounds · 9e8912e0
      Linus Torvalds authored
      
      
      In order for ntpd to correctly synchronize the clocks, the frequency of
      the system clock must not be off by more than 500 ppm (or, put another
      way, 1:2000), or ntpd will end up giving up on trying to synchronize
      properly, and ends up reseting the clock in jumps instead.
      
      The fast TSC PIT calibration sometimes failed this test - it was
      assuming that the PIT reads always took about one microsecond each (2us
      for the two reads to get a 16-bit timer), and that calibrating TSC to
      the PIT over 15ms should thus be sufficient to get much closer than
      500ppm (max 2us error on both sides giving 4us over 15ms: a 270 ppm
      error value).
      
      However, that assumption does not always hold: apparently some hardware
      is either very much slower at reading the PIT registers, or there was
      other noise causing at least one machine to get 700+ ppm errors.
      
      So instead of using a fixed 15ms timing loop, this changes the fast PIT
      calibration to read the TSC delta over the individual PIT timer reads,
      and use the result to calculate the error bars on the PIT read timing
      properly.  We then successfully calibrate the TSC only if the maximum
      error bars fall below 500ppm.
      
      In the process, we also relax the timing to allow up to 25ms for the
      calibration, although it can happen much faster depending on hardware.
      Reported-and-tested-by: default avatarJesper Krogh <jesper@krogh.cc>
      Cc: john stultz <johnstul@us.ibm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Acked-by: default avatarIngo Molnar <mingo@elte.hu>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      9e8912e0
    • Linus Torvalds's avatar
      Fix potential fast PIT TSC calibration startup glitch · a6a80e1d
      Linus Torvalds authored
      
      
      During bootup, when we reprogram the PIT (programmable interval timer)
      to start counting down from 0xffff in order to use it for the fast TSC
      calibration, we should also make sure to delay a bit afterwards to allow
      the PIT hardware to actually start counting with the new value.
      
      That will happens at the next CLK pulse (1.193182 MHz), so the easiest
      way to do that is to just wait at least one microsecond after
      programming the new PIT counter value.  We do that by just reading the
      counter value back once - which will take about 2us on PC hardware.
      Reported-and-tested-by: default avatarjohn stultz <johnstul@us.ibm.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      a6a80e1d
  6. 16 Mar, 2009 8 commits
  7. 13 Mar, 2009 2 commits
  8. 12 Mar, 2009 13 commits