1. 22 Oct, 2009 1 commit
  2. 14 Oct, 2009 7 commits
  3. 12 Oct, 2009 3 commits
    • Nitin Gupta's avatar
      ARM: force dcache flush if dcache_dirty bit set · 787b2faa
      Nitin Gupta authored
      On ARM, update_mmu_cache() does dcache flush for a page only if
      it has a kernel mapping (page_mapping(page) != NULL). The correct
      behavior would be to force the flush based on dcache_dirty bit only.
      One of the cases where present logic would be a problem is when
      a RAM based block device[1] is used as a swap disk. In this case,
      we would have in-memory data corruption as shown in steps below:
          - Allocate a new page (if not already in swap cache)
          - Issue read from swap disk
              - Block driver issues flush_dcache_page()
              - flush_dcache_page() simply sets PG_dcache_dirty bit and does not
                actually issue a flush since this page has no user space mapping yet.
          - Now, if swap disk is almost full, this newly read page is removed
            from swap cache and corrsponding swap slot is freed.
          - Map this page anonymously in user space.
          - update_mmu_cache()
              - Since this page does not have kernel mapping (its not in page/swap
                cache and is mapped anonymously), it does not issue dcache flush
                even if dcache_dirty bit is set by flush_dcache_page() above.
          <user now gets stale data since dcache was never flushed>
      Same problem exists on mips too.
      [1] example:
       - brd (RAM based block device)
       - ramzswap (RAM based compressed swap device)
      Signed-off-by: default avatarNitin Gupta <ngupta@vflare.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
    • Dennis O'Brien's avatar
      [ARM] pxa: workaround errata #37 by not using half turbo switching · 4367216a
      Dennis O'Brien authored
      PXA27x Errata #37 implies system will hang when switching into or out of
      half turbo (HT bit in CLKCFG) mode, workaround this by not using it.
      Signed-off-by: default avatarDennis O'Brien <dennis.obrien@eqware.net>
      Cc: stable-2.6.31 <stable@kernel.org>
      Signed-off-by: default avatarEric Miao <eric.y.miao@gmail.com>
    • Julia Lawall's avatar
      [ARM] pxa/csb726: adjust duplicate structure field initialization · c639ef43
      Julia Lawall authored
      Currently the irq_type field of the csb726_lan_config structure is
      initialized twice.  The value in the first case,
      SMSC911X_IRQ_POLARITY_ACTIVE_LOW, is normally stored in the irq_polarity
      field, so I have renamed the field in the first initialization to that.
      Signed-off-by: default avatarJulia Lawall <julia@diku.dk>
      Signed-off-by: default avatarEric Miao <eric.y.miao@gmail.com>
  4. 11 Oct, 2009 6 commits
  5. 10 Oct, 2009 3 commits
  6. 07 Oct, 2009 10 commits
  7. 06 Oct, 2009 3 commits
  8. 05 Oct, 2009 7 commits
    • Amit Kucheria's avatar
      Input: fix rx51 board keymap · acf442dc
      Amit Kucheria authored
      The original driver was written with the KEY() macro defined as (col,
      row) instead of (row, col) as defined by the matrix keypad
      infrastructure. So the keymap was defined accordingly. Since the
      driver that was merged upstream uses the matrix keypad infrastructure,
      modify the keymap accordingly.
      While we are at it, fix the comments in twl4030.h and define
      PERSISTENT_KEY as (r,c) instead of (c, r)
      Tested on a RX51 (N900) device.
      Signed-off-by: default avatarAmit Kucheria <amit.kucheria@verdurent.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarDmitry Torokhov <dtor@mail.ru>
    • Rajendra Nayak's avatar
      omap: Lock DPLL5 at boot · 7a66a39b
      Rajendra Nayak authored
      Lock DPLL5 at 120MHz at boot. The USBHOST 120MHz f-clock and
      USBTLL f-clock are the only users of this DPLL, and 120MHz is
      is the only recommended rate for these clocks.
      With this patch, the 60 MHz ULPI clock is generated correctly.
      Tested on an OMAP3430 SDP.
      Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
      Signed-off-by: default avatarAnand Gadiyar <gadiyar@ti.com>
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
    • Tony Lindgren's avatar
      omap: Fix incorrect 730 vs 850 detection · a9f82d10
      Tony Lindgren authored
      Commit cd922049
      support for omap850. However, the patch accidentally
      removed the wrong ifdef:
       #  define cpu_is_omap730()		1
       # endif
      +# if defined(CONFIG_ARCH_OMAP850)
      +#  undef  cpu_is_omap850
      +#  define cpu_is_omap850()		1
      +# endif
       void omap2_check_revision(void);
       #endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
      Instead of removing removing the #endif at the end of the file,
      the #endif before #else should have been removed.
      But we cannot have multiple #else statements as pointed out by
      Alistair Buxton <a.j.buxton@gmail.com>. So the fix is to:
      - remove the non-multi-omap special handling, as we need to
        detect between omap730 and omap850 anyways.
      - add the missing #endif back to the end of the file
      Reported-by: default avatarSanjeev Premi <premi@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
    • Artem Bityutskiy's avatar
      OMAP3: PM: introduce a new powerdomain walk helper · ee894b18
      Artem Bityutskiy authored
      The 'pwrdm_for_each()' function walks powerdomains with a spinlock
      locked, so the the callbacks cannot do anything which may sleep.
      This patch introduces a 'pwrdm_for_each_nolock()' helper which does
      the same, but without the spinlock locked. This fixes the following
      lockdep warning:
      [    0.000000] WARNING: at kernel/lockdep.c:2460 lockdep_trace_alloc+0xac/0xec()
      [    0.000000] Modules linked in:
      (unwind_backtrace+0x0/0xdc) from [<c0045464>] (warn_slowpath_common+0x48/0x60)
      (warn_slowpath_common+0x48/0x60) from [<c0067dd4>] (lockdep_trace_alloc+0xac/0xec)
      (lockdep_trace_alloc+0xac/0xec) from [<c009da14>] (kmem_cache_alloc+0x1c/0xd0)
      (kmem_cache_alloc+0x1c/0xd0) from [<c00b21d8>] (d_alloc+0x1c/0x1a4)
      (d_alloc+0x1c/0x1a4) from [<c00a887c>] (__lookup_hash+0xd8/0x118)
      (__lookup_hash+0xd8/0x118) from [<c00a9f20>] (lookup_one_len+0x84/0x94)
      (lookup_one_len+0x84/0x94) from [<c010d12c>] (debugfs_create_file+0x8c/0x20c)
      (debugfs_create_file+0x8c/0x20c) from [<c010d320>] (debugfs_create_dir+0x1c/0x20)
      (debugfs_create_dir+0x1c/0x20) from [<c000e8cc>] (pwrdms_setup+0x60/0x90)
      (pwrdms_setup+0x60/0x90) from [<c002e010>] (pwrdm_for_each+0x30/0x80)
      (pwrdm_for_each+0x30/0x80) from [<c000e79c>] (pm_dbg_init+0x7c/0x14c)
      (pm_dbg_init+0x7c/0x14c) from [<c00232b4>] (do_one_initcall+0x5c/0x1b8)
      (do_one_initcall+0x5c/0x1b8) from [<c00083f8>] (kernel_init+0x90/0x10c)
      (kernel_init+0x90/0x10c) from [<c00242c4>] (kernel_thread_exit+0x0/0x8)
      Signed-off-by: default avatarArtem Bityutskiy <Artem.Bityutskiy@nokia.com>
      Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
    • Kevin Hilman's avatar
      OMAP3: PM: Enable GPIO module-level wakeups · eb350f74
      Kevin Hilman authored
      Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
      enabled as wakups.  This patch also enables GPIOs in the PER
      powerdomain (banks 2-6) to be used as possible wakeup sources.
      In addition, this patch ensures that all GPIO wakeups can wakeup
      the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
      NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
      enables the per-bank wakeups at the powerdomain level.
      This problem was discovered by Mike Chan when preventing the CORE
      powerdomain from going into retention/off.  When CORE was allowed to
      hit retention, GPIO wakeups via IO pad were working fine, but when
      CORE remained on, GPIO module-level wakeups were not working properly.
      To test, prevent CORE from going inactive/retention/off, thus
      preventing the IO chain from being armed:
        # echo 3 > /debug/pm_debug/core_pwrdm/suspend
      This ensures that GPIO wakeups happen via module-level wakeups and
      not via IO pad.
      Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
      Tested on Zoom2 using the QUART interrup GPIO  (gpio 102, in PER)
      Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
      Reported-by: default avatarMike Chan <mikechan@google.com>
      Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
    • Vikram Pandita's avatar
      OMAP3: PM: USBHOST: clear wakeup events on both hosts · 71a80775
      Vikram Pandita authored
      USBHOST module has 2 fclocks (for HOST1 and HOST2), only one iclock
      and only a single bit in the WKST register to indicate a wakeup event.
      Because of the single WKST bit, we cannot know whether a wakeup event
      was on HOST1 or HOST2, so enable both fclocks before clearing the
      wakeup event to ensure both hosts can properly clear the event.
      Signed-off-by: default avatarVikram Pandita <vikram.pandita@ti.com>
      Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
    • Paul Walmsley's avatar
      OMAP3: PM: PRCM interrupt: only handle selected PRCM interrupts · 8cb0ac99
      Paul Walmsley authored
      Clearing wakeup sources is now only done when the PRM indicates a
      wakeup source interrupt.  Since we don't handle any other types of
      PRCM interrupts right now, warn if we get any other type of PRCM
      interrupt.  Either code needs to be added to the PRCM interrupt
      handler to react to these, or these other interrupts should be masked
      off at init.
      Updated after Jon Hunter's PRCM IRQ rework by Kevin Hilman.
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>