1. 06 Jan, 2011 2 commits
  2. 05 Jan, 2011 1 commit
  3. 02 Jan, 2011 1 commit
  4. 24 Dec, 2010 1 commit
    • eric miao's avatar
      ARM: 6532/1: Allow machine to specify it's own IRQ handlers at run-time · 52108641
      eric miao authored
      
      
      Normally different ARM platform has different way to decode the IRQ
      hardware status and demultiplex to the corresponding IRQ handler.
      This is highly optimized by macro irq_handler in entry-armv.S, and
      each machine defines their own macro to decode the IRQ number.
      However, this prevents multiple machine classes to be built into a
      single kernel.
      
      By allowing each machine to specify thier own handler, and making
      function pointer 'handle_arch_irq' to point to it at run time, this
      can be solved. And introduce CONFIG_MULTI_IRQ_HANDLER to allow both
      solutions to work.
      
      Comparing with the highly optimized macro of irq_handler, the new
      function must be written with care not to lose too much performance.
      And the IPI stuff on SMP is expected to move to the provided arch
      IRQ handler as well.
      
      The assembly code to invoke handle_arch_irq is optimized by Russell
      King.
      Signed-off-by: default avatarEric Miao <eric.miao@canonical.com>
      Acked-by: default avatarNicolas Pitre <nicolas.pitre@linaro.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      52108641
  5. 22 Dec, 2010 11 commits
  6. 21 Dec, 2010 1 commit
  7. 20 Dec, 2010 3 commits
    • Shawn Guo's avatar
    • Dave Martin's avatar
      ARM: 6516/1: Allow SMP_ON_UP to work with Thumb-2 kernels. · ed3768a8
      Dave Martin authored
      
      
        * __fixup_smp_on_up has been modified with support for the
          THUMB2_KERNEL case.  For THUMB2_KERNEL only, fixups are split
          into halfwords in case of misalignment, since we can't rely on
          unaligned accesses working before turning the MMU on.
      
          No attempt is made to optimise the aligned case, since the
          number of fixups is typically small, and it seems best to keep
          the code as simple as possible.
      
        * Add a rotate in the fixup_smp code in order to support
          CPU_BIG_ENDIAN, as suggested by Nicolas Pitre.
      
        * Add an assembly-time sanity-check to ALT_UP() to ensure that
          the content really is the right size (4 bytes).
      
          (No check is done for ALT_SMP().  Possibly, this could be fixed
          by splitting the two uses ot ALT_SMP() (ALT_SMP...SMP_UP versus
          ALT_SMP...SMP_UP_B) into two macros.  In the first case,
          ALT_SMP needs to expand to >= 4 bytes, not == 4.)
      
        * smp_mpidr.h (which implements ALT_SMP()/ALT_UP() manually due
          to macro limitations) has not been modified: the affected
          instruction (mov) has no 16-bit encoding, so the correct
          instruction size is satisfied in this case.
      
        * A "mode" parameter has been added to smp_dmb:
      
          smp_dmb arm @ assumes 4-byte instructions (for ARM code, e.g. kuser)
          smp_dmb     @ uses W() to ensure 4-byte instructions for ALT_SMP()
      
          This avoids assembly failures due to use of W() inside smp_dmb,
          when assembling pure-ARM code in the vectors page.
      
          There might be a better way to achieve this.
      
        * Kconfig: make SMP_ON_UP depend on
          (!THUMB2_KERNEL || !BIG_ENDIAN) i.e., THUMB2_KERNEL is now
          supported, but only if !BIG_ENDIAN (The fixup code for Thumb-2
          currently assumes little-endian order.)
      
      Tested using a single generic realview kernel on:
      	ARM RealView PB-A8 (CONFIG_THUMB2_KERNEL={n,y})
      	ARM RealView PBX-A9 (SMP)
      Signed-off-by: default avatarDave Martin <dave.martin@linaro.org>
      Acked-by: default avatarNicolas Pitre <nicolas.pitre@linaro.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      ed3768a8
    • Haojian Zhuang's avatar
      ARM: pxa: add iwmmx support for PJ4 · ef6c8445
      Haojian Zhuang authored
      
      
      iwmmxt is used in XScale, XScale3, Mohawk and PJ4 core. But the instructions
      of accessing CP0 and CP1 is changed in PJ4. Append more files to support
      iwmmxt in PJ4 core.
      Signed-off-by: default avatarZhou Zhu <zzhu3@marvell.com>
      Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@marvell.com>
      Acked-by: default avatarNicolas Pitre <nico@fluxnic.net>
      Signed-off-by: default avatarEric Miao <eric.y.miao@gmail.com>
      ef6c8445
  8. 14 Dec, 2010 2 commits
  9. 09 Dec, 2010 1 commit
  10. 05 Dec, 2010 2 commits
  11. 04 Dec, 2010 1 commit
  12. 30 Nov, 2010 2 commits
  13. 26 Nov, 2010 1 commit
  14. 22 Nov, 2010 2 commits
  15. 19 Nov, 2010 1 commit
    • Rabin Vincent's avatar
      ARM: ftrace: enable function graph tracer · 0e341af8
      Rabin Vincent authored
      
      
      Add the options to enable the function graph tracer on ARM.  Function
      graph tracer support requires frame pointers, so exclude Thumb-2 and
      also make sure FRAME_POINTER gets enabled when FUNCTION_GRAPH_TRACER is
      used, since FUNCTION_TRACER doesn't "select FRAME_POINTER" when
      ARM_UNWIND is used.  Therefore, with GCC 4.4.0+, you get plain function
      tracing without frame pointers, but you'll need them if you want
      function graph tracing.
      Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarRabin Vincent <rabin@rab.in>
      0e341af8
  16. 16 Nov, 2010 1 commit
    • Paul Mundt's avatar
      ARM: mach-shmobile: Tidy up the Kconfig bits. · 6d72ad35
      Paul Mundt authored
      
      
      Presently each one of the CPUs manually selects the same feature set, and
      there's a reasonable expectation that none of these will change for
      future CPUs in the SH-Mobile / R-Mobile family, so we move those over to
      the top-level ARCH_SHMOBILE.
      
      While we're at it, all of the CPUs support optional GPIOs via the PFC,
      do not have I/O ports, and expect sparse IRQ, so we bring the
      configuration in line across the board.
      
      This more or less brings the ARM-based parts in sync with their SH
      counterparts.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      6d72ad35
  17. 13 Nov, 2010 3 commits
  18. 07 Nov, 2010 1 commit
  19. 25 Oct, 2010 2 commits
  20. 22 Oct, 2010 1 commit