1. 02 Mar, 2013 28 commits
    • James Hogan's avatar
      metag: Atomics, locks and bitops · 6006c0d8
      James Hogan authored
      
      
      Add header files to implement Meta hardware thread locks (used by some
      other atomic operations), atomics, spinlocks, and bitops.
      
      There are 2 main types of atomic primitives for metag (in addition to
      IRQs off on UP):
       - LOCK instructions provide locking between hardware threads.
       - LNKGET/LNKSET instructions provide load-linked/store-conditional
         operations allowing for lighter weight atomics on Meta2
      
      LOCK instructions allow for hardware threads to acquire voluntary or
      exclusive hardware thread locks:
       - LOCK0 releases exclusive and voluntary lock from the running hardware
         thread.
       - LOCK1 acquires the voluntary hardware lock, blocking until it becomes
         available.
       - LOCK2 implies LOCK1, and additionally acquires the exclusive hardware
         lock, blocking all other hardware threads from executing.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      6006c0d8
    • James Hogan's avatar
      metag: Module support · 9b802d1f
      James Hogan authored
      
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      9b802d1f
    • James Hogan's avatar
      metag: Scheduling/Process management · 44dea393
      James Hogan authored
      
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      44dea393
    • James Hogan's avatar
      metag: System Calls · 26025bbf
      James Hogan authored
      
      
      Add metag system call and gateway page interfaces. The metag
      architecture port uses the generic system call numbers from
      asm-generic/unistd.h, as well as a user gateway page mapped at
      0x6ffff000 which contains fast atomic primitives (depending on SMP) and
      a fast method of accessing TLS data.
      
      System calls use the SWITCH instruction with the immediate 0x440001 to
      signal a system call.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      26025bbf
    • James Hogan's avatar
      metag: Internal and external irqchips · 5698c50d
      James Hogan authored
      
      
      Meta core internal interrupts (from HWSTATMETA and friends) are vectored
      onto the TR1 core trigger for the current thread. This is demultiplexed
      in irq-metag.c to individual Linux IRQs for each internal interrupt.
      
      External SoC interrupts (from HWSTATEXT and friends) are vectored onto
      the TR2 core trigger for the current thread. This is demultiplexed in
      irq-metag-ext.c to individual Linux IRQs for each external SoC interrupt.
      The external irqchip has devicetree bindings for configuring the number
      of irq banks and the type of masking available.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Rob Landley <rob@landley.net>
      Cc: Dom Cobley <popcornmix@gmail.com>
      Cc: Simon Arlott <simon@fire.lp0.eu>
      Cc: Viresh Kumar <viresh.kumar@linaro.org>
      Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
      Cc: devicetree-discuss@lists.ozlabs.org
      Cc: linux-doc@vger.kernel.org
      5698c50d
    • James Hogan's avatar
      metag: IRQ handling · 63047ea3
      James Hogan authored
      
      
      Add core IRQ handling for metag. The code in irq.c exposes the TBX
      signal numbers as Linux IRQs.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      63047ea3
    • James Hogan's avatar
      metag: Traps · ac919f08
      James Hogan authored
      
      
      Add trap code for metag. At the lowest level Meta traps (and return from
      interrupt instruction - RTI) simply swap the PC and PCX registers and
      optionally toggle the interrupt status bit (ISTAT). Low level TBX code
      in tbipcx.S handles the core context save, determine the TBX signal
      number based on the core trigger that fired (using the TXSTATI status
      register), and call TBX signal handlers (mostly in traps.c) via a vector
      table.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Al Viro <viro@zeniv.linux.org.uk>
      ac919f08
    • James Hogan's avatar
      metag: Time keeping · a2c5d4ed
      James Hogan authored
      
      
      Add time keeping code for metag. Meta hardware threads have 2 timers.
      The background timer (TXTIMER) is used as a free-running time base, and
      the interrupt timer (TXTIMERI) is used for the timer interrupt. Both
      counters traditionally count at approximately 1MHz.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: John Stultz <johnstul@us.ibm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      a2c5d4ed
    • James Hogan's avatar
      metag: ptrace · bc3966bf
      James Hogan authored
      
      
      The ptrace interface for metag provides access to some core register
      sets using the PTRACE_GETREGSET and PTRACE_SETREGSET operations. The
      details of the internal context structures is abstracted into user API
      structures to both ease use and allow flexibility to change the internal
      context layouts. Copyin and copyout functions for these register sets
      are exposed to allow signal handling code to use them to copy to and
      from the signal context.
      
      struct user_gp_regs (NT_PRSTATUS) provides access to the core general
      purpose register context.
      
      struct user_cb_regs (NT_METAG_CBUF) provides access to the TXCATCH*
      registers which contains information abuot a memory fault, unaligned
      access error or watchpoint. This can be modified to alter the way the
      fault is replayed on resume ("catch replay"), or to prevent the replay
      taking place.
      
      struct user_rp_state (NT_METAG_RPIPE) provides access to the state of
      the Meta read pipeline which can be used to hide memory latencies in
      hand optimised data loops.
      
      Extended DSP register state, DSP RAM, and hardware breakpoint registers
      aren't yet exposed through ptrace.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Denys Vlasenko <vda.linux@googlemail.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
      bc3966bf
    • James Hogan's avatar
      metag: Device tree · 29dd78cf
      James Hogan authored
      
      
      Add device tree files to arch/metag.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Reviewed-by: default avatarVineet Gupta <vgupta@synopsys.com>
      29dd78cf
    • James Hogan's avatar
      metag: Signal handling · 262d96b0
      James Hogan authored
      
      
      Add signal handling code for metag.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Al Viro <viro@zeniv.linux.org.uk>
      262d96b0
    • James Hogan's avatar
      metag: TCM support · c438b58e
      James Hogan authored
      
      
      Add some TCM support
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      c438b58e
    • James Hogan's avatar
      metag: Highmem support · bbc17704
      James Hogan authored
      
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      bbc17704
    • James Hogan's avatar
      metag: Huge TLB · e624e95b
      James Hogan authored
      
      
      Add huge TLB support to the metag architecture.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      e624e95b
    • James Hogan's avatar
      metag: Memory handling · 373cd784
      James Hogan authored
      
      
      Meta has instructions for accessing:
       - bytes        - GETB (1 byte)
       - words        - GETW (2 bytes)
       - doublewords  - GETD (4 bytes)
       - longwords    - GETL (8 bytes)
      
      All accesses must be aligned. Unaligned accesses can be detected and
      made to fault on Meta2, however it isn't possible to fix up unaligned
      writes so we don't bother fixing up reads either.
      
      This patch adds metag memory handling code including:
       - I/O memory (io.h, ioremap.c): Actually any virtual memory can be
         accessed with these helpers. A part of the non-MMUable address space
         is used for memory mapped I/O. The ioremap() function is implemented
         one to one for non-MMUable addresses.
       - User memory (uaccess.h, usercopy.c): User memory is directly
         accessible from privileged code.
       - Kernel memory (maccess.c): probe_kernel_write() needs to be
         overwridden to use the I/O functions when doing a simple aligned
         write to non-writecombined memory, otherwise the write may be split
         by the generic version.
      
      Note that due to the fact that a portion of the virtual address space is
      non-MMUable, and therefore always maps directly to the physical address
      space, metag specific I/O functions are made available (metag_in32,
      metag_out32 etc). These cast the address argument to a pointer so that
      they can be used with raw physical addresses. These accessors are only
      to be used for accessing fixed core Meta architecture registers in the
      non-MMU region, and not for any SoC/peripheral registers.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      373cd784
    • James Hogan's avatar
      metag: Memory management · f5df8e26
      James Hogan authored
      
      
      Add memory management files for metag.
      
      Meta's 32bit virtual address space is split into two halves:
       - local (0x08000000-0x7fffffff): traditionally local to a hardware
         thread and incoherent between hardware threads. Each hardware thread
         has it's own local MMU table. On Meta2 the local space can be
         globally coherent (GCOn) if the cache partitions coincide.
       - global (0x88000000-0xffff0000): coherent and traditionally global
         between hardware threads. On Meta2, each hardware thread has it's own
         global MMU table.
      
      The low 128MiB of each half is non-MMUable and maps directly to the
      physical address space:
       - 0x00010000-0x07ffffff: contains Meta core registers and maps SoC bus
       - 0x80000000-0x87ffffff: contains low latency global core memories
      
      Linux usually further splits the local virtual address space like this:
       - 0x08000000-0x3fffffff: user mappings
       - 0x40000000-0x7fffffff: kernel mappings
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      f5df8e26
    • James Hogan's avatar
      metag: Cache/TLB handling · 99ef7c2a
      James Hogan authored
      
      
      Add cache and TLB handling code for metag, including the required
      callbacks used by MM switches and DMA operations. Caches can be
      partitioned between the hardware threads and the global space, however
      this is usually configured by the bootloader so Linux doesn't make any
      changes to this configuration. TLBs aren't configurable, so only need
      consideration to flush them.
      
      On Meta1 the L1 cache was VIVT which required a full flush on MM switch.
      Meta2 has a VIPT L1 cache so it doesn't require the full flush on MM
      switch. Meta2 can also have a writeback L2 with hardware prefetch which
      requires some special handling. Support is optional, and the L2 can be
      detected and initialised by Linux.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      99ef7c2a
    • James Hogan's avatar
      metag: TBX source · 027f891f
      James Hogan authored
      
      
      Add source files from the Thread Binary Interface (TBI) library which
      provides useful low level operations and traps/context management.
      
      Among other things it handles interrupt/exception/syscall entry (in
      tbipcx.S).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      027f891f
    • James Hogan's avatar
      metag: TBX header · 4ca151b2
      James Hogan authored
      
      
      Add the main header for the Thread Binary Interface (TBI) library which
      provides useful low level operations and trap/context management.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      4ca151b2
    • James Hogan's avatar
      metag: Boot · 85d9d7a9
      James Hogan authored
      
      
      Add boot code for metag. Due to the multi-threaded nature of Meta it is
      not uncommon for an RTOS or bare metal application to be started on
      other hardware threads by the bootloader. Since there is a single MMU
      switch which affects all threads, the MMU is traditionally configured by
      the bootloader prior to starting Linux. The bootloader passes a
      structure to Linux which among other things contains information about
      memory regions which have been mapped. Linux then assumes control of the
      local heap memory region.
      
      A kernel arguments string pointer or a flattened device tree pointer can
      be provided in the third argument.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      85d9d7a9
    • James Hogan's avatar
      metag: Header for core memory mapped registers · 87aa1328
      James Hogan authored
      
      
      Add the header <asm/metag_mem.h> describing addresses, fields, and bits
      of various core memory mapped registers in the low non-MMU region.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      87aa1328
    • James Hogan's avatar
      metag: Headers for core arch constants · af8a1049
      James Hogan authored
      
      
      Add a couple of header files containing core architecture constants.
      
      The first (<asm/metag_isa.h>) contains some constants relating to the
      instruction set, such as values to give to the CACHEW and CACHER
      instructions.
      
      The second (<asm/metag_regs.h>) contains constants for the core register
      units directly accessible to various instructions, and for the
      registers, fields, and bits in those units. The main units described are
      the control unit (CT.*), the trigger unit (TR.*), and the run-time trace
      unit (TT.*).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      af8a1049
    • James Hogan's avatar
      metag: Add MAINTAINERS entry · 12285945
      James Hogan authored
      
      
      Add MAINTAINERS entry for the metag architecture port.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Mauro Carvalho Chehab <mchehab@redhat.com>
      Cc: Cesar Eduardo Barros <cesarb@cesarb.net>
      Cc: Joe Perches <joe@perches.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      12285945
    • James Hogan's avatar
      trace/ring_buffer: handle 64bit aligned structs · 649508f6
      James Hogan authored
      
      
      Some 32 bit architectures require 64 bit values to be aligned (for
      example Meta which has 64 bit read/write instructions). These require 8
      byte alignment of event data too, so use
      !CONFIG_HAVE_64BIT_ALIGNED_ACCESS instead of !CONFIG_64BIT ||
      CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS to decide alignment, and align
      buffer_data_page::data accordingly.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Ingo Molnar <mingo@redhat.com>
      Acked-by: Steven Rostedt <rostedt@goodmis.org> (previous version subtly different)
      649508f6
    • James Hogan's avatar
      Add HAVE_64BIT_ALIGNED_ACCESS · c19fa94a
      James Hogan authored
      
      
      On 64 bit architectures with no efficient unaligned access, padding and
      explicit alignment must be added in various places to prevent unaligned
      64bit accesses (such as taskstats and trace ring buffer).
      
      However this also needs to apply to 32 bit architectures with 64 bit
      accesses requiring alignment such as metag.
      
      This is solved by adding a new Kconfig symbol HAVE_64BIT_ALIGNED_ACCESS
      which defaults to 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS, and can be
      explicitly selected by METAG and any other relevant architectures. This
      can be used in various places to determine whether 64bit alignment is
      required.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Al Viro <viro@zeniv.linux.org.uk>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Eric Paris <eparis@redhat.com>
      Cc: Will Drewry <wad@chromium.org>
      c19fa94a
    • James Hogan's avatar
      Revert some of "binfmt_elf: cleanups" · c07380be
      James Hogan authored
      The commit "binfmt_elf: cleanups"
      (f670d0ec
      
      ) removed an ifndef elf_map but
      this breaks compilation for metag which does define elf_map.
      
      This adds the ifndef back in as it was before, but does not affect the
      other cleanups made by that patch.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Alexander Viro <viro@zeniv.linux.org.uk>
      Cc: linux-fsdevel@vger.kernel.org
      Acked-by: default avatarMikael Pettersson <mikpe@it.uu.se>
      c07380be
    • James Hogan's avatar
      asm-generic/unistd.h: handle symbol prefixes in cond_syscall · 4dd3c959
      James Hogan authored
      
      
      Some architectures have symbol prefixes and set CONFIG_SYMBOL_PREFIX,
      but this wasn't taken into account by the generic cond_syscall. It's
      easy enough to fix in a generic fashion, so add the symbol prefix to
      symbol names in cond_syscall when CONFIG_SYMBOL_PREFIX is set.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
      4dd3c959
    • James Hogan's avatar
      asm-generic/io.h: check CONFIG_VIRT_TO_BUS · c93d0312
      James Hogan authored
      
      
      Make asm-generic/io.h check CONFIG_VIRT_TO_BUS before defining
      virt_to_bus() and bus_to_virt(), otherwise it's easy to accidentally
      have a silently failing incorrect direct mapped definition rather then
      no definition at all.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
      c93d0312
  2. 18 Feb, 2013 3 commits
  3. 15 Feb, 2013 7 commits
  4. 14 Feb, 2013 2 commits