1. 21 Dec, 2010 1 commit
    • Magnus Damm's avatar
      ARM: mach-shmobile: sh73a0 INTCS support · 5f53a56a
      Magnus Damm authored
      Add INTCS support for the sh73a0 processor.
      
      The interrupts on the sh73a0 processor are managed
      through controllers such as GIC, INTCS and INTCA.
      
      The ARM cores use the GIC as primary interrupt
      controller and the INTCS and INTCA are hanging off
      the GIC as cascaded interrupt controllers.
      
      Peripherals connected both to the GIC and the INTC
      controllers should if possible only use the GIC.
      
      If no GIC connection is available then INTCS and
      INTCA may be used instead.
      Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      5f53a56a
  2. 20 Dec, 2010 1 commit
  3. 17 Dec, 2010 2 commits
    • Magnus Damm's avatar
      ARM: mach-shmobile: INTC interrupt priority level demux fix · 1cf215a5
      Magnus Damm authored
      Fix interrupt priority level handling on SH-Mobile ARM.
      
      SH-Mobile ARM platforms using multiple interrupt priority
      levels need this patch to fix a potential dead lock that
      may occur if multiple interrupts with different levels
      are pending simultaneously.
      
      The default INTC configuration is to use the same priority
      level for all interrupts, so this issue does not trigger by
      default. It is however common for board code to override the
      interrupt priority for certain interrupt sources depending
      on the application. Without this fix such boards may lock up.
      
      In detail, this patch updates the INTC code in entry-macro.S
      to make sure that the INTLVLA register gets set as expected.
      
      To trigger this bug modify the board specific code to adjust
      the interrupt priority level for the ethernet chip. After
      changing the priority level simply use flood ping to drown
      the board with interrupts.
      
      This patch applies to INTCA-based processors such as sh7372,
      sh7377 and sh7372. GIC-based processors are not affected.
      
      Suitable for v2.6.37-rc and stable from v2.6.34 to v2.6.36.
      
      Cc: stable@kernel.org
      Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
      Tested-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      1cf215a5
    • Magnus Damm's avatar
      ARM: mach-shmobile: fix compile warning in mm/init.c · 676b14c3
      Magnus Damm authored
      Turn down the warning noise from the compiler,
      basically a SH-Mobile specific version of the
      patch located in the RMK patch tracker:
      
      6484/1: "fix compile warning in mm/init.c",
      
      Without this patch the following warning triggers:
      
       CC      arch/arm/kernel/sys_arm.o
      arch/arm/mm/init.c: In function 'mem_init':
      arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int'
        CC      arch/arm/kernel/traps.o
      Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      676b14c3
  4. 14 Dec, 2010 1 commit
  5. 12 Dec, 2010 1 commit
  6. 08 Dec, 2010 1 commit
  7. 03 Dec, 2010 1 commit
  8. 30 Nov, 2010 2 commits
  9. 29 Nov, 2010 1 commit
  10. 28 Nov, 2010 6 commits
  11. 25 Nov, 2010 3 commits
  12. 23 Nov, 2010 10 commits
  13. 19 Nov, 2010 2 commits
  14. 18 Nov, 2010 1 commit
  15. 17 Nov, 2010 2 commits
    • Magnus Damm's avatar
      ARM: mach-shmobile: Initial AG5 and AG5EVM support · 6d9598e2
      Magnus Damm authored
      This patch adds initial support for Renesas SH-Mobile AG5.
      
      At this point the AG5 CPU support is limited to the ARM
      core, SCIF serial and a CMT timer together with L2 cache
      and the GIC. The AG5EVM board also supports Ethernet.
      
      Future patches will add support for GPIO, INTCS, CPGA
      and platform data / driver updates for devices such as
      IIC, LCDC, FSI, KEYSC, CEU and SDHI among others.
      
      The code in entry-macro.S will be cleaned up when the
      ARM IRQ demux code improvements have been merged.
      
      Depends on the AG5EVM mach-type recently registered but
      not yet present in arch/arm/tools/mach-types.
      
      As the AG5EVM board comes with 512MiB memory it is
      recommended to turn on HIGHMEM.
      
      Many thanks to Yoshii-san for initial bring up.
      Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      6d9598e2
    • Magnus Damm's avatar
      ARM: mach-shmobile: sh7372 USB0/IIC1 MSTP fix · 4d048435
      Magnus Damm authored
      Fix a MSTP assignment problem in the sh7372 clock
      framework code. The USB drivers should attach to
      MSTP322 not MSTP33 where IIC1 is located.
      Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      4d048435
  16. 16 Nov, 2010 1 commit
    • Paul Mundt's avatar
      ARM: mach-shmobile: Tidy up the Kconfig bits. · 6d72ad35
      Paul Mundt authored
      Presently each one of the CPUs manually selects the same feature set, and
      there's a reasonable expectation that none of these will change for
      future CPUs in the SH-Mobile / R-Mobile family, so we move those over to
      the top-level ARCH_SHMOBILE.
      
      While we're at it, all of the CPUs support optional GPIOs via the PFC,
      do not have I/O ports, and expect sparse IRQ, so we bring the
      configuration in line across the board.
      
      This more or less brings the ARM-based parts in sync with their SH
      counterparts.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      6d72ad35
  17. 15 Nov, 2010 1 commit
  18. 14 Nov, 2010 1 commit
  19. 07 Nov, 2010 2 commits