1. 15 Jan, 2015 1 commit
  2. 07 Jan, 2015 1 commit
  3. 25 Nov, 2014 4 commits
    • Mark Rutland's avatar
      arm64: sanity checks: add ID_AA64DFR{0,1}_EL1 · 3eebdbe5
      Mark Rutland authored
      While we currently expect self-hosted debug support to be identical
      across CPUs, we don't currently sanity check this.
      
      This patch adds logging of the ID_AA64DFR{0,1}_EL1 values and associated
      sanity checking code.
      
      It's not clear to me whether we need to check PMUVer, TraceVer, and
      DebugVer, as we don't currently rely on these fields at all.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      3eebdbe5
    • Mark Rutland's avatar
      arm64: sanity checks: add missing newline to print · efdf4211
      Mark Rutland authored
      A missing newline in the WARN_TAINT_ONCE string results in ugly and
      somewhat difficult to read output in the case of a sanity check failure,
      as the next print does not appear on a new line:
      
        Unsupported CPU feature variation.Modules linked in:
      
      This patch adds the missing newline, fixing the output formatting.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      efdf4211
    • Mark Rutland's avatar
      arm64: sanity checks: ignore ID_MMFR0.AuxReg · 9760270c
      Mark Rutland authored
      It seems that Cortex-A53 r0p4 added support for AIFSR and ADFSR, and
      ID_MMFR0.AuxReg has been updated accordingly to report this fact. As
      Cortex-A53 could be paired with CPUs which do not implement these
      registers (e.g. all current revisions of Cortex-A57), this may trigger a
      sanity check failure at boot.
      
      The AuxReg value describes the availability of the ACTLR, AIFSR, and
      ADFSR registers, which are only of use to 32-bit guest OSs, and have
      IMPLEMENTATION DEFINED contents. Given the nature of these registers it
      is likely that KVM will need to trap accesses regardless of whether the
      CPUs are heterogeneous.
      
      This patch masks out the ID_MMFR0.AuxReg value from the sanity checks,
      preventing spurious warnings at boot time.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reported-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      9760270c
    • Andre Przywara's avatar
      arm64: detect silicon revisions and set cap bits accordingly · e116a375
      Andre Przywara authored
      After each CPU has been started, we iterate through a list of
      CPU features or bugs to detect CPUs which need (or could benefit
      from) kernel code patches.
      For each feature/bug there is a function which checks if that
      particular CPU is affected. We will later provide some more generic
      functions for common things like testing for certain MIDR ranges.
      We do this for every CPU to cover big.LITTLE systems properly as
      well.
      If a certain feature/bug has been detected, the capability bit will
      be set, so that later the call to apply_alternatives() will trigger
      the actual code patching.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      e116a375
  4. 08 Sep, 2014 2 commits
  5. 18 Aug, 2014 1 commit
  6. 01 Aug, 2014 1 commit
    • Mark Rutland's avatar
      arm64: add newline to I-cache policy string · ea171967
      Mark Rutland authored
      Due to a missing newline in the I-cache policy detection log output,
      it's possible to get some ratehr unfortunate output at boot time:
      
      CPU1: Booted secondary processor
      Detected VIPT I-cache on CPU1CPU2: Booted secondary processor
      Detected VIPT I-cache on CPU2CPU3: Booted secondary processor
      Detected VIPT I-cache on CPU3CPU4: Booted secondary processor
      Detected PIPT I-cache on CPU4CPU5: Booted secondary processor
      Detected PIPT I-cache on CPU5Brought up 6 CPUs
      SMP: Total of 6 processors activated.
      
      This patch adds the missing newline to the format string, cleaning up
      the output.
      
      Fixes: 59ccc0d4 ("arm64: cachetype: report weakest cache policy")
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      ea171967
  7. 18 Jul, 2014 3 commits
    • Mark Rutland's avatar
      arm64: add runtime system sanity checks · 127161aa
      Mark Rutland authored
      Unexpected variation in certain system register values across CPUs is an
      indicator of potential problems with a system. The kernel expects CPUs
      to be mostly identical in terms of supported features, even in systems
      with heterogeneous CPUs, with uniform instruction set support being
      critical for the correct operation of userspace.
      
      To help detect issues early where hardware violates the expectations of
      the kernel, this patch adds simple runtime sanity checks on important ID
      registers in the bring up path of each CPU.
      
      Where CPUs are fundamentally mismatched, set TAINT_CPU_OUT_OF_SPEC.
      Given that the kernel assumes CPUs are identical feature wise, let's not
      pretend that we expect such configurations to work. Supporting such
      configurations would require massive rework, and hopefully they will
      never exist.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      127161aa
    • Mark Rutland's avatar
      arm64: cachetype: report weakest cache policy · 59ccc0d4
      Mark Rutland authored
      In big.LITTLE systems, the I-cache policy may differ across CPUs, and
      thus we must always meet the most stringent maintenance requirements of
      any I-cache in the system when performing maintenance to ensure
      correctness. Unfortunately this requirement is not met as we always look
      at the current CPU's cache type register to determine the maintenance
      requirements.
      
      This patch causes the I-cache policy of all CPUs to be taken into
      account for icache_is_aliasing and icache_is_aivivt. If any I-cache in
      the system is aliasing or AIVIVT, the respective function will return
      true. At boot each CPU may set flags to identify that at least one
      I-cache in the system is aliasing and/or AIVIVT.
      
      The now unused and potentially misleading icache_policy function is
      removed.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      59ccc0d4
    • Mark Rutland's avatar
      arm64: cpuinfo: record cpu system register values · df857416
      Mark Rutland authored
      Several kernel subsystems need to know details about CPU system register
      values, sometimes for CPUs other than that they are executing on. Rather
      than hard-coding system register accesses and cross-calls for these
      cases, this patch adds logic to record various system register values at
      boot-time. This may be used for feature reporting, firmware bug
      detection, etc.
      
      Separate hooks are added for the boot and hotplug paths to enable
      one-time intialisation and cold/warm boot value mismatch detection in
      later patches.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      df857416