1. 07 Jun, 2010 1 commit
  2. 21 May, 2010 1 commit
  3. 18 May, 2010 2 commits
  4. 02 Apr, 2010 1 commit
  5. 25 Mar, 2010 2 commits
  6. 24 Mar, 2010 2 commits
    • Clemens Ladisch's avatar
      PCI quirk: RS780/RS880: work around missing MSI initialization · a5ee4eb7
      Clemens Ladisch authored
      
      
      AMD says in section 2.5.4 (GFX MSI Enable) of #43291 (AMD 780G Family
      Register Programming Requirements):
      
        The SBIOS must enable internal graphics MSI capability in GCCFG by
        setting the following: NBCFG.NB_CNTL.STRAP_MSI_ENABLE='1'
      
      Quite a few BIOS writers misinterpret this sentence and think that
      enabling MSI is an optional feature.  However, clearing that bit just
      prevents delivery of MSI messages but does not remove the MSI PCI
      capabilities registers, and so leaves these devices unusable for any
      driver that attempts to use MSI.
      
      Setting that bit is not possible after the BIOS has locked down the
      configuration registers, so we have to manually disable MSI for the
      affected devices.
      
      This fixes the codec communication errors in the HDA driver when
      accessing the HDMI audio device, and allows us to get rid of the
      overcautious quirk in radeon_irq_kms.c.
      Signed-off-by: default avatarClemens Ladisch <clemens@ladisch.de>
      Tested-by: default avatarAlex Deucher <alexdeucher@gamil.com>
      Cc: <stable@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      a5ee4eb7
    • Tim Yamin's avatar
      PCI quirk: only apply CX700 PCI bus parking quirk if external VT6212L is present · ca846392
      Tim Yamin authored
      
      
      Apply the CX700 quirk only when an external VT6212L is present (which
      is the case for the errant hardware the quirk was written for), don't
      touch the settings otherwise -- Hauppage PVR-500 tuners need PCI Bus
      Parking in order to work and when that's turned on everything seems
      to behave fine.
      
      I guess the underlying problem is a combination of an external VT6212L
      and the CX700 rather than the CX700's PCI being broken completely for
      all cases...
      Reported-by: default avatarJeroen Roos <jeroen@roosnl.com>
      Signed-off-by: default avatarTim Yamin <plasm@roo.me.uk>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      ca846392
  7. 06 Mar, 2010 1 commit
  8. 22 Feb, 2010 2 commits
  9. 05 Feb, 2010 1 commit
    • Andres Salomon's avatar
      CS5536: apply pci quirk for BIOS SMBUS bug · 73d2eaac
      Andres Salomon authored
      
      
      The new cs5535-* drivers use PCI header config info rather than MSRs to
      determine the memory region to use for things like GPIOs and MFGPTs.  As
      anticipated, we've run into a buggy BIOS:
      
      [    0.081818] pci 0000:00:14.0: reg 10: [io  0x6000-0x7fff]
      [    0.081906] pci 0000:00:14.0: reg 14: [io  0x6100-0x61ff]
      [    0.082015] pci 0000:00:14.0: reg 18: [io  0x6200-0x63ff]
      [    0.082917] pci 0000:00:14.2: reg 20: [io  0xe000-0xe00f]
      [    0.083551] pci 0000:00:15.0: reg 10: [mem 0xa0010000-0xa0010fff]
      [    0.084436] pci 0000:00:15.1: reg 10: [mem 0xa0011000-0xa0011fff]
      [    0.088816] PCI: pci_cache_line_size set to 32 bytes
      [    0.088938] pci 0000:00:14.0: address space collision: [io 0x6100-0x61ff] already in use
      [    0.089052] pci 0000:00:14.0: can't reserve [io  0x6100-0x61ff]
      
      This is a Soekris board, and its BIOS sets the size of the PCI ISA bridge
      device's BAR0 to 8k.  In reality, it should be 8 bytes (BAR0 is used for
      SMBus stuff).  This quirk checks for an incorrect size, and resets it
      accordingly.
      Signed-off-by: default avatarAndres Salomon <dilinger@collabora.co.uk>
      Tested-by: default avatarLeigh Porter <leigh@leighporter.org>
      Tested-by: default avatarJens Rottmann <JRottmann@LiPPERTEmbedded.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      73d2eaac
  10. 31 Dec, 2009 2 commits
  11. 16 Dec, 2009 4 commits
  12. 04 Nov, 2009 3 commits
  13. 16 Oct, 2009 1 commit
  14. 12 Oct, 2009 3 commits
  15. 07 Oct, 2009 1 commit
  16. 14 Sep, 2009 1 commit
  17. 11 Sep, 2009 1 commit
  18. 09 Sep, 2009 4 commits
  19. 29 Jun, 2009 1 commit
    • Alan Cox's avatar
      PCI: More PATA quirks for not entering D3 · 7a661c6f
      Alan Cox authored
      
      
      The ALi loses some state if it goes into D3. Unfortunately even with the
      chipset documents I can't figure out how to restore some bits of it.
      
      The VIA one saves/restores apparently fine but the ACPI _GTM methods break
      on some platforms if we do this and this causes cable misdetections.
      
      These are both effectively regressions as historically nothing matched the
      devices and then decided not to bind to them. Nowdays something is binding
      to all sorts of devices and a result they get dumped into D3.
      Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
      Acked-by: default avatarJeff Garzik <jeff@garzik.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      7a661c6f
  20. 16 Jun, 2009 2 commits
  21. 11 Jun, 2009 1 commit
  22. 06 May, 2009 1 commit
  23. 22 Apr, 2009 1 commit
  24. 06 Apr, 2009 1 commit