1. 20 Dec, 2011 1 commit
  2. 06 Dec, 2011 1 commit
  3. 11 Nov, 2011 1 commit
  4. 18 Oct, 2011 1 commit
  5. 10 Oct, 2011 2 commits
    • Alex Deucher's avatar
      drm/radeon/kms: set DMA mask properly on newer PCI asics · 005a83f1
      Alex Deucher authored
      If a card wasn't PCIE, we always set the DMA mask to 32 bits.
      This is only applies to the old rage128/r1xx gart block on
      early radeon asics (~r1xx-r4xx).  Newer PCI and IGP cards
      can handle 40 bits just fine.
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      Cc: Chen Jie <chenj@lemote.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
    • Michael Witten's avatar
      Michael Witten authored
      The value of RADEON_DEBUGFS_MAX_NUM_FILES has been used to
      specify the size of an array, each element of which looks
      like this:
        struct radeon_debugfs {
                struct drm_info_list    *files;
                unsigned                num_files;
      Consequently, the number of debugfs files may be much greater
      than RADEON_DEBUGFS_MAX_NUM_FILES, something that the current
      code ignores:
        if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
                DRM_ERROR("Reached maximum number of debugfs files.\n");
                DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
                return -EINVAL;
      This commit fixes this make, and accordingly renames:
      Signed-off-by: default avatarMichael Witten <mfwitten@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  6. 22 Aug, 2011 1 commit
  7. 12 Aug, 2011 1 commit
  8. 04 Aug, 2011 1 commit
  9. 16 Jun, 2011 1 commit
  10. 08 Jun, 2011 1 commit
  11. 01 Jun, 2011 1 commit
  12. 23 May, 2011 1 commit
  13. 31 Mar, 2011 1 commit
  14. 02 Mar, 2011 1 commit
  15. 22 Feb, 2011 2 commits
  16. 13 Feb, 2011 1 commit
    • Dave Airlie's avatar
      drm/radeon: fix race between GPU reset and TTM delayed delete thread. · 8fd1b84c
      Dave Airlie authored
      My evergreen has been in a remote PC for week and reset has never once
      saved me from certain doom, I finally relocated to the box with a
      serial cable and noticed an oops when the GPU resets, and the TTM
      delayed delete thread tries to remove something from the GTT.
      This stops the delayed delete thread from executing across the GPU
      reset handler, and woot I can GPU reset now.
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  17. 25 Jan, 2011 1 commit
    • Torben Hohn's avatar
      console: rename acquire/release_console_sem() to console_lock/unlock() · ac751efa
      Torben Hohn authored
      The -rt patches change the console_semaphore to console_mutex.  As a
      result, a quite large chunk of the patches changes all
      acquire/release_console_sem() to acquire/release_console_mutex()
      This commit makes things use more neutral function names which dont make
      implications about the underlying lock.
      The only real change is the return value of console_trylock which is
      inverted from try_acquire_console_sem()
      This patch also paves the way to switching console_sem from a semaphore to
      a mutex.
      [akpm@linux-foundation.org: coding-style fixes]
      [akpm@linux-foundation.org: make console_trylock return 1 on success, per Geert]
      Signed-off-by: default avatarTorben Hohn <torbenh@gmx.de>
      Cc: Thomas Gleixner <tglx@tglx.de>
      Cc: Greg KH <gregkh@suse.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
  18. 06 Jan, 2011 2 commits
  19. 05 Jan, 2011 1 commit
    • Tejun Heo's avatar
      drm/radeon: use system_wq instead of dev_priv->wq · 32c87fca
      Tejun Heo authored
      With cmwq, there's no reason for radeon to use a dedicated workqueue.
      Drop dev_priv->wq and use system_wq instead.
      Because radeon_driver_irq_uninstall_kms() may be called from
      unsleepable context, the work items can't be flushed from there.
      Instead, init and flush from radeon_irq_kms_init/fini().
      While at it, simplify canceling/flushing of rdev->pm.dynpm_idle_work.
      Always initialize and sync cancel instead of being unnecessarily smart
      about it.
      Signed-off-by: default avatarTejun Heo <tj@kernel.org>
      Acked-by: default avatarAlex Deucher <alexdeucher@gmail.com>
      Cc: dri-devel@lists.freedesktop.org
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  20. 04 Jan, 2011 2 commits
  21. 20 Dec, 2010 1 commit
  22. 15 Dec, 2010 1 commit
  23. 07 Dec, 2010 1 commit
  24. 22 Nov, 2010 1 commit
  25. 17 Nov, 2010 1 commit
  26. 05 Oct, 2010 2 commits
    • Alex Deucher's avatar
      drm/radeon/kms/r6xx+: use new style fencing (v3) · d0f8a854
      Alex Deucher authored
      On r6xx+ a newer fence mechanism was implemented to replace
      the old wait_until plus scratch regs setup.  A single EOP event
      will flush the destination caches, write a fence value, and generate
      an interrupt.  This is the recommended fence mechanism on r6xx+ asics.
      This requires my previous writeback patch.
      v2: fix typo that enabled event fence checking on all asics
      rather than just r6xx+.
      v3: properly enable EOP interrupts
      Should fix:
      Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
    • Alex Deucher's avatar
      drm/radeon/kms: enable writeback (v2) · 724c80e1
      Alex Deucher authored
      When writeback is enabled, the GPU shadows writes to certain
      registers into a buffer in memory.  The driver can then read
      the values from the shadow rather than reading back from the
      register across the bus.  Writeback can be disabled by setting
      the no_wb module param to 1.
      On r6xx/r7xx/evergreen, the following registers are shadowed:
      - CP scratch registers
      - CP read pointer
      - IH write pointer
      On r1xx-rr5xx, the following registers are shadowed:
      - CP scratch registers
      - CP read pointer
      - Combine wb patches for r6xx-evergreen and r1xx-r5xx
      - Writeback is disabled on AGP boards since it tends to be
      unreliable on AGP using the gart.
      - Check radeon_wb_init return values properly.
      Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  27. 29 Aug, 2010 1 commit
  28. 19 Aug, 2010 1 commit
  29. 11 Aug, 2010 1 commit
  30. 01 Aug, 2010 2 commits
  31. 15 Jul, 2010 1 commit
    • Alex Deucher's avatar
      drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asics · 8d369bb1
      Alex Deucher authored
      The asics in question have the following requirements with regard to
      their gart setups:
      1. The GART aperture size has to be in the form of 2^X bytes, where X is from 25 to 31
      2. The GART aperture MC base has to be aligned to a boundary equal to the size of the
      3. The GART page table has to be aligned to the boundary equal to the size of the table.
      4. The GART page table size is: table_entry_size * (aperture_size / page_size)
      5. The GART page table has to be allocated in non-paged, non-cached, contiguous system
      This patch takes care 2.  The rest should already be handled properly.
      This fixes a regression noticed by: Torsten Kaiser <just.for.lkml@googlemail.com>
      Tested-by: default avatarTorsten Kaiser <just.for.lkml@googlemail.com>
      Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
  32. 30 Jun, 2010 1 commit
  33. 02 Jun, 2010 1 commit
  34. 31 May, 2010 1 commit