1. 27 Jun, 2006 2 commits
  2. 20 Jun, 2006 1 commit
    • Benjamin Herrenschmidt's avatar
      [POWERPC] cell: add RAS support · acf7d768
      Benjamin Herrenschmidt authored
      
      
      This is a first version of support for the Cell BE "Reliability,
      Availability and Serviceability" features.
      
      It doesn't yet handle some of the RAS interrupts (the ones described in
      iic_is/iic_irr), I'm still working on a proper way to expose these. They
      are essentially a cascaded controller by themselves (sic !) though I may
      just handle them locally to the iic driver. I need also to sync with
      David Erb on the way he hooked in the performance monitor interrupt.
      
      So that's all for 2.6.17 and I'll do more work on that with my rework of
      the powerpc interrupt layer that I'm hacking on at the moment.
      Signed-off-by: default avatarArnd Bergmann <arnd.bergmann@de.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      acf7d768
  3. 18 Apr, 2006 1 commit
    • Paul Mackerras's avatar
      powerpc: Use correct sequence for putting CPU into nap mode · f39224a8
      Paul Mackerras authored
      
      
      We weren't using the recommended sequence for putting the CPU into
      nap mode.  When I changed the idle loop, for some reason 7447A cpus
      started hanging when we put them into nap mode.  Changing to the
      recommended sequence fixes that.
      
      The complexity here is that the recommended sequence is a loop that
      keeps putting the cpu back into nap mode.  Clearly we need some way
      to break out of the loop when an interrupt (external interrupt,
      decrementer, performance monitor) occurs.  Here we use a bit in
      the thread_info struct to indicate that we need this, and the exception
      entry code notices this and arranges for the exception to return
      to the value in the link register, thus breaking out of the loop.
      We use a new `local_flags' field in the thread_info which we can
      alter without needing to use an atomic update sequence.
      
      The PPC970 has the same recommended sequence, so we do the same thing
      there too.
      
      This also fixes a bug in the kernel stack overflow handling code on
      32-bit, since it was causing a value that we needed in a register to
      get trashed.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      f39224a8
  4. 26 Mar, 2006 2 commits
    • Anton Blanchard's avatar
      [PATCH] powerpc: Allow non zero boot cpuids · 4df20460
      Anton Blanchard authored
      
      
      We currently have a hack to flip the boot cpu and its secondary thread
      to logical cpuid 0 and 1. This means the logical - physical mapping will
      differ depending on which cpu is boot cpu. This is most apparent on
      kexec, where we might kexec on any cpu and therefore change the mapping
      from boot to boot.
      
      The patch below does a first pass early on to work out the logical cpuid
      of the boot thread. We then fix up some paca structures to match.
      
      Ive also removed the boot_cpuid_phys variable for ppc64, to be
      consistent we use get_hard_smp_processor_id(boot_cpuid) everywhere.
      Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      4df20460
    • Olaf Hering's avatar
      [PATCH] correct the comment about stackpointer alignment in __boot_from_prom · 6088857b
      Olaf Hering authored
      
      
      The address of variable val in prom_init_stdout is passed to prom_getprop.
      prom_getprop casts the pointer to u32 and passes it to call_prom in the hope
      that OpenFirmware stores something there.
      But the pointer is truncated in the lower bits and the expected value is
      stored somewhere else.
      
      In my testing I had a stackpointer of 0x0023e6b4. val was at offset 120,
      wich has address 0x0023e72c. But the value passed to OF was 0x0023e728.
      
      c00000000040b710:       3b 01 00 78     addi    r24,r1,120
      ...
      c00000000040b754:       57 08 00 38     rlwinm  r8,r24,0,0,28
      ...
      c00000000040b784:       80 01 00 78     lwz     r0,120(r1)
      ...
      c00000000040b798:       90 1b 00 0c     stw     r0,12(r27)
      ...
      
      The stackpointer came from 32bit code.
      The chain was yaboot -> zImage -> vmlinux
      
      PowerMac OpenFirmware does appearently not handle the ELF sections
      correctly.  If yaboot was compiled in
      /usr/src/packages/BUILD/lilo-10.1.1/yaboot, then the stackpointer is
      unaligned. But the stackpointer is correct if yaboot is compiled in
      /tmp/yaboot.
      
      This bug triggered since 2.6.15, now prom_getprop is an inline
      function. gcc clears the lower bits, instead of just clearing the
      upper 32 bits.
      Signed-off-by: default avatarOlaf Hering <olh@suse.de>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      6088857b
  5. 04 Mar, 2006 1 commit
  6. 23 Feb, 2006 3 commits
    • Paul Mackerras's avatar
      powerpc: Implement accurate task and CPU time accounting · c6622f63
      Paul Mackerras authored
      
      
      This implements accurate task and cpu time accounting for 64-bit
      powerpc kernels.  Instead of accounting a whole jiffy of time to a
      task on a timer interrupt because that task happened to be running at
      the time, we now account time in units of timebase ticks according to
      the actual time spent by the task in user mode and kernel mode.  We
      also count the time spent processing hardware and software interrupts
      accurately.  This is conditional on CONFIG_VIRT_CPU_ACCOUNTING.  If
      that is not set, we do tick-based approximate accounting as before.
      
      To get this accurate information, we read either the PURR (processor
      utilization of resources register) on POWER5 machines, or the timebase
      on other machines on
      
      * each entry to the kernel from usermode
      * each exit to usermode
      * transitions between process context, hard irq context and soft irq
        context in kernel mode
      * context switches.
      
      On POWER5 systems with shared-processor logical partitioning we also
      read both the PURR and the timebase at each timer interrupt and
      context switch in order to determine how much time has been taken by
      the hypervisor to run other partitions ("steal" time).  Unfortunately,
      since we need values of the PURR on both threads at the same time to
      accurately calculate the steal time, and since we can only calculate
      steal time on a per-core basis, the apportioning of the steal time
      between idle time (time which we ceded to the hypervisor in the idle
      loop) and actual stolen time is somewhat approximate at the moment.
      
      This is all based quite heavily on what s390 does, and it uses the
      generic interfaces that were added by the s390 developers,
      i.e. account_system_time(), account_user_time(), etc.
      
      This patch doesn't add any new interfaces between the kernel and
      userspace, and doesn't change the units in which time is reported to
      userspace by things such as /proc/stat, /proc/<pid>/stat, getrusage(),
      times(), etc.  Internally the various task and cpu times are stored in
      timebase units, but they are converted to USER_HZ units (1/100th of a
      second) when reported to userspace.  Some precision is therefore lost
      but there should not be any accumulating error, since the internal
      accumulation is at full precision.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      c6622f63
    • Anton Blanchard's avatar
      [PATCH] powerpc64: remove broken/bitrotted HMT support · f1870f77
      Anton Blanchard authored
      
      
      HMT support is currently broken and needs to be reworked to play nicely
      with the SMT scheduler. Remove the bit rotten bits for the time being.
      
      I also updated an incorrect comment, we enter __secondary_hold with the
      physical cpu id in r3.
      Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      f1870f77
    • Anton Blanchard's avatar
      [PATCH] powerpc: Fix runlatch performance issues · cb2c9b27
      Anton Blanchard authored
      
      
      The runlatch SPR can take a lot of time to write. My original runlatch
      code would set it on every exception entry even though most of the time
      this was not required. It would also continually set it in the idle
      loop, which is an issue on an SMT capable processor.
      
      Now we cache the runlatch value in a threadinfo bit, and only check for
      it in decrementer and hardware interrupt exceptions as well as the idle
      loop. Boot on POWER3, POWER5 and iseries, and compile tested on pmac32.
      Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      cb2c9b27
  7. 19 Feb, 2006 1 commit
  8. 09 Feb, 2006 1 commit
  9. 07 Feb, 2006 1 commit
  10. 13 Jan, 2006 2 commits
    • David Gibson's avatar
      [PATCH] powerpc: Remove lppaca structure from the PACA · 3356bb9f
      David Gibson authored
      
      
      At present the lppaca - the structure shared with the iSeries
      hypervisor and phyp - is contained within the PACA, our own low-level
      per-cpu structure.  This doesn't have to be so, the patch below
      removes it, making a separate array of lppaca structures.
      
      This saves approximately 500*NR_CPUS bytes of image size and kernel
      memory, because we don't need aligning gap between the Linux and
      hypervisor portions of every PACA.  On the other hand it means an
      extra level of dereference in many accesses to the lppaca.
      
      The patch also gets rid of several places where we assign the paca
      address to a local variable for no particular reason.
      Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      3356bb9f
    • David Gibson's avatar
      [PATCH] powerpc: Cleanup LOADADDR etc. asm macros · e58c3495
      David Gibson authored
      
      
      This patch consolidates the variety of macros used for loading 32 or
      64-bit constants in assembler (LOADADDR, LOADBASE, SET_REG_TO_*).  The
      idea is to make the set of macros consistent across 32 and 64 bit and
      to make it more obvious which is the appropriate one to use in a given
      situation.  The new macros and their semantics are described in the
      comments in ppc_asm.h.
      
      In the process, we change several places that were unnecessarily using
      immediate loads on ppc64 to use the GOT/TOC.  Likewise we cleanup a
      couple of places where we were clumsily subtracting PAGE_OFFSET with
      asm instructions to use assemble-time arithmetic or the toreal() macro
      instead.
      Signed-off-by: default avatarDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      e58c3495
  11. 09 Jan, 2006 1 commit
  12. 08 Jan, 2006 5 commits
  13. 09 Nov, 2005 1 commit
  14. 06 Nov, 2005 1 commit
    • Benjamin Herrenschmidt's avatar
      [PATCH] ppc64: support 64k pages · 3c726f8d
      Benjamin Herrenschmidt authored
      
      
      Adds a new CONFIG_PPC_64K_PAGES which, when enabled, changes the kernel
      base page size to 64K.  The resulting kernel still boots on any
      hardware.  On current machines with 4K pages support only, the kernel
      will maintain 16 "subpages" for each 64K page transparently.
      
      Note that while real 64K capable HW has been tested, the current patch
      will not enable it yet as such hardware is not released yet, and I'm
      still verifying with the firmware architects the proper to get the
      information from the newer hypervisors.
      Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      3c726f8d
  15. 03 Nov, 2005 1 commit
  16. 01 Nov, 2005 1 commit
  17. 22 Oct, 2005 1 commit
    • Paul Mackerras's avatar
      powerpc: Merge in 64-bit powermac support. · 35499c01
      Paul Mackerras authored
      
      
      This brings in a lot of changes from arch/ppc64/kernel/pmac_*.c to
      arch/powerpc/platforms/powermac/*.c and makes various minor tweaks
      elsewhere.  On the powermac we now initialize ppc_md by copying
      the whole pmac_md structure into it, which required some changes in
      the ordering of initializations of individual fields of it.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      35499c01
  18. 21 Oct, 2005 1 commit
    • David Gibson's avatar
      [PATCH] powerpc: Merge thread_info.h · 6cb7bfeb
      David Gibson authored
      
      
      Merge ppc32 and ppc64 versions of thread_info.h.  They were pretty
      similar already, the chief changes are:
      
      	- Instead of inline asm to implement current_thread_info(),
      which needs to be different for ppc32 and ppc64, we use C with an
      asm("r1") register variable.  gcc turns it into the same asm as we
      used to have for both platforms.
      	- We replace ppc32's 'local_flags' with the ppc64
      'syscall_noerror' field.  The noerror flag was in fact the only thing
      in the local_flags field anyway, so the ppc64 approach is simpler, and
      means we only need a load-immediate/store instead of load/mask/store
      when clearing the flag.
      	- In readiness for 64k pages, when THREAD_SIZE will be less
      than a page, ppc64 used kmalloc() rather than get_free_pages() to
      allocate the kernel stack.  With this patch we do the same for ppc32,
      since there's no strong reason not to.
      	- For ppc64, we no longer export THREAD_SHIFT and THREAD_SIZE
      via asm-offsets, thread_info.h can now be safely included in asm, as
      on ppc32.
      
      Built and booted on G4 Powerbook (ARCH=ppc and ARCH=powerpc) and
      Power5 (ARCH=ppc64 and ARCH=powerpc).
      Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      6cb7bfeb
  19. 10 Oct, 2005 2 commits
  20. 09 Oct, 2005 1 commit
  21. 05 Oct, 2005 1 commit
  22. 30 Sep, 2005 1 commit
  23. 26 Sep, 2005 1 commit
    • Paul Mackerras's avatar
      powerpc: Merge enough to start building in arch/powerpc. · 14cf11af
      Paul Mackerras authored
      
      
      This creates the directory structure under arch/powerpc and a bunch
      of Kconfig files.  It does a first-cut merge of arch/powerpc/mm,
      arch/powerpc/lib and arch/powerpc/platforms/powermac.  This is enough
      to build a 32-bit powermac kernel with ARCH=powerpc.
      
      For now we are getting some unmerged files from arch/ppc/kernel and
      arch/ppc/syslib, or arch/ppc64/kernel.  This makes some minor changes
      to files in those directories and files outside arch/powerpc.
      
      The boot directory is still not merged.  That's going to be interesting.
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      14cf11af
  24. 22 Sep, 2005 2 commits
  25. 21 Sep, 2005 1 commit
  26. 15 Sep, 2005 1 commit
  27. 09 Sep, 2005 1 commit
  28. 06 Sep, 2005 1 commit
  29. 29 Aug, 2005 1 commit
    • Stephen Rothwell's avatar
      [PATCH] fix iSeries build for gcc-3.4 · 1e4a79e0
      Stephen Rothwell authored
      gcc 3.4 (at least the build we are using) puts the gcc generated .ident
      string into a .note section at the end of the files it compiles (gcc
      3.3.3-hammer and gcc 4.0.2 Debian puts it in the .text section).  This
      means that the lparmap.s file we produce in the iSeries build may end with
      a .note section.  When we include it into head.S, the assembler can no
      longer resolve some of the conditional branches since the target label
      ends up too far away.  This patch just forces us back to the .text section
      after including lparmap.s.
      
      The breakage was caused by my patch "iSeries build with newer assemblers
      and compilers" (sha1-id: 2ad56496
      
      ).
      Signed-off-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
      1e4a79e0