1. 12 May, 2015 1 commit
  2. 30 Apr, 2015 2 commits
  3. 24 Mar, 2015 1 commit
    • Will Deacon's avatar
      arm64: pmu: add support for interrupt-affinity property · d5efd9cc
      Will Deacon authored
      Historically, the PMU devicetree bindings have expected SPIs to be
      listed in order of *logical* CPU number. This is problematic for
      bootloaders, especially when the boot CPU (logical ID 0) isn't listed
      first in the devicetree.
      This patch adds a new optional property, interrupt-affinity, to the
      PMU node which allows the interrupt affinity to be described using
      a list of phandled to CPU nodes, with each entry in the list
      corresponding to the SPI at the same index in the interrupts property.
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  4. 19 Mar, 2015 1 commit
    • Suzuki K. Poulose's avatar
      arm64: perf: reject groups spanning multiple HW PMUs · 8fff105e
      Suzuki K. Poulose authored
      The perf core implicitly rejects events spanning multiple HW PMUs, as in
      these cases the event->ctx will differ. However this validation is
      performed after pmu::event_init() is called in perf_init_event(), and
      thus pmu::event_init() may be called with a group leader from a
      different HW PMU.
      The ARM64 PMU driver does not take this fact into account, and when
      validating groups assumes that it can call to_arm_pmu(event->pmu) for
      any HW event. When the event in question is from another HW PMU this is
      wrong, and results in dereferencing garbage.
      This patch updates the ARM64 PMU driver to first test for and reject
      events from other PMUs, moving the to_arm_pmu and related logic after
      this test. Fixes a crash triggered by perf_fuzzer on Linux-4.0-rc2, with
      a CCI PMU present:
      Bad mode in Synchronous Abort handler detected, code 0x86000006 -- IABT (current EL)
      CPU: 0 PID: 1371 Comm: perf_fuzzer Not tainted 3.19.0+ #249
      Hardware name: V2F-1XV7 Cortex-A53x2 SMM (DT)
      task: ffffffc07c73a280 ti: ffffffc07b0a0000 task.ti: ffffffc07b0a0000
      PC is at 0x0
      LR is at validate_event+0x90/0xa8
      pc : [<0000000000000000>] lr : [<ffffffc000090228>] pstate: 00000145
      sp : ffffffc07b0a3ba0
      [<          (null)>]           (null)
      [<ffffffc0000907d8>] armpmu_event_init+0x174/0x3cc
      [<ffffffc00015d870>] perf_try_init_event+0x34/0x70
      [<ffffffc000164094>] perf_init_event+0xe0/0x10c
      [<ffffffc000164348>] perf_event_alloc+0x288/0x358
      [<ffffffc000164c5c>] SyS_perf_event_open+0x464/0x98c
      Code: bad PC value
      Also cleans up the code to use the arm_pmu only when we know
      that we are dealing with an arm pmu event.
      Cc: Will Deacon <will.deacon@arm.com>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarPeter Ziljstra (Intel) <peterz@infradead.org>
      Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  5. 04 Dec, 2014 1 commit
    • Daniel Thompson's avatar
      arm64: perf: Prevent wraparound during overflow · cbbf2e6e
      Daniel Thompson authored
      If the overflow threshold for a counter is set above or near the
      0xffffffff boundary then the kernel may lose track of the overflow
      causing only events that occur *after* the overflow to be recorded.
      Specifically the problem occurs when the value of the performance counter
      overtakes its original programmed value due to wrap around.
      Typical solutions to this problem are either to avoid programming in
      values likely to be overtaken or to treat the overflow bit as the 33rd
      bit of the counter.
      Its somewhat fiddly to refactor the code to correctly handle the 33rd bit
      during irqsave sections (context switches for example) so instead we take
      the simpler approach of avoiding values likely to be overtaken.
      We set the limit to half of max_period because this matches the limit
      imposed in __hw_perf_event_init(). This causes a doubling of the interrupt
      rate for large threshold values, however even with a very fast counter
      ticking at 4GHz the interrupt rate would only be ~1Hz.
      Signed-off-by: default avatarDaniel Thompson <daniel.thompson@linaro.org>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  6. 03 Oct, 2014 1 commit
  7. 06 Apr, 2014 1 commit
    • Mark Salter's avatar
      arm64: fix !CONFIG_COMPAT build failures · ff268ff7
      Mark Salter authored
      Recent arm64 builds using CONFIG_ARM64_64K_PAGES are failing with:
        arch/arm64/kernel/perf_regs.c: In function ‘perf_reg_abi’:
        arch/arm64/kernel/perf_regs.c:41:2: error: implicit declaration of function ‘is_compat_thread’
        arch/arm64/kernel/perf_event.c:1398:2: error: unknown type name ‘compat_uptr_t’
      This is due to some recent arm64 perf commits with compat support:
        commit 23c7d70d:
          ARM64: perf: add support for frame pointer unwinding in compat mode
        commit 2ee0d7fd
          ARM64: perf: add support for perf registers API
      Those patches make the arm64 kernel unbuildable if CONFIG_COMPAT is not
      defined and CONFIG_ARM64_64K_PAGES depends on !CONFIG_COMPAT. This patch
      allows the arm64 kernel to build with and without CONFIG_COMPAT.
      Signed-off-by: default avatarMark Salter <msalter@redhat.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
  8. 13 Mar, 2014 1 commit
  9. 19 Dec, 2013 1 commit
  10. 29 Oct, 2013 1 commit
  11. 25 Oct, 2013 1 commit
  12. 20 Aug, 2013 4 commits
  13. 20 Jun, 2013 1 commit
  14. 29 Jan, 2013 1 commit
  15. 03 Jan, 2013 1 commit
    • Greg Kroah-Hartman's avatar
      ARCH: drivers remove __dev* attributes. · b881bc46
      Greg Kroah-Hartman authored
      This fixes up all of the smaller arches that had __dev* markings for
      their platform-specific drivers.
      CONFIG_HOTPLUG is going away as an option.  As a result, the __dev*
      markings need to be removed.
      This change removes the use of __devinit, __devexit_p, __devinitdata,
      __devinitconst, and __devexit from these drivers.
      Based on patches originally written by Bill Pemberton, but redone by me
      in order to handle some of the coding style issues better, by hand.
      Cc: Bill Pemberton <wfp5p@virginia.edu>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
      Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: Jesper Nilsson <jesper.nilsson@axis.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Hirokazu Takata <takata@linux-m32r.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
      Cc: Jonas Bonn <jonas@southpole.se>
      Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
      Cc: Helge Deller <deller@gmx.de>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Chen Liqin <liqin.chen@sunplusct.com>
      Cc: Lennox Wu <lennox.wu@gmail.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Chris Metcalf <cmetcalf@tilera.com>
      Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
      Cc: Bob Liu <lliubbo@gmail.com>
      Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Myron Stowe <myron.stowe@redhat.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Andi Kleen <ak@linux.intel.com>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: Thierry Reding <thierry.reding@avionic-design.de>
      Cc: Greg Ungerer <gerg@uclinux.org>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Cc: "Srivatsa S. Bhat" <srivatsa.bhat@linux.vnet.ibm.com>
      Cc: Mark Salter <msalter@redhat.com>
      Cc: Yong Zhang <yong.zhang0@gmail.com>
      Cc: Michael Holzheu <holzheu@linux.vnet.ibm.com>
      Cc: Cornelia Huck <cornelia.huck@de.ibm.com>
      Cc: Jan Glauber <jang@linux.vnet.ibm.com>
      Cc: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
      Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
  16. 08 Nov, 2012 1 commit
    • Will Deacon's avatar
      arm64: perf: use architected event for CPU cycle counter · f46f979f
      Will Deacon authored
      We currently use a fake event encoding (0xFF) to indicate CPU cycles so
      that we don't waste an event counter and can target the hardware cycle
      counter instead.
      The problem with this approach is that the event space defined by the
      architecture permits an implementation to allocate 0xFF for some other
      This patch uses the architected cycle counter encoding (0x11) so that
      we avoid potentially clashing with event encodings on future CPU
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
  17. 17 Sep, 2012 1 commit