1. 02 Jun, 2015 2 commits
  2. 26 Mar, 2015 1 commit
  3. 03 Feb, 2015 1 commit
    • Paul Walmsley's avatar
      Documentation: DT bindings: add more Tegra chip compatible strings · 193c9d23
      Paul Walmsley authored
      Align compatible strings for several IP blocks present on Tegra chips
      with the latest doctrine from the DT maintainers:
      
      http://marc.info/?l=devicetree&m=142255654213019&w=2
      
      The primary objective here is to avoid checkpatch warnings, per:
      
      http://marc.info/?l=linux-tegra&m=142201349727836&w=2
      
      
      
      DT binding text files have been updated for the following IP blocks:
      
      - PCIe
      - SOR
      - SoC timers
      - AHB "gizmo"
      - APB_MISC
      - pinmux control
      - UART
      - PWM
      - I2C
      - SPI
      - RTC
      - PMC
      - eFuse
      - AHCI
      - HDA
      - XUSB_PADCTRL
      - SDHCI
      - SOC_THERM
      - AHUB
      - I2S
      - EHCI
      - USB PHY
      
      N.B. The nvidia,tegra20-timer compatible string is removed from the
      nvidia,tegra30-timer.txt documentation file because it's already
      mentioned in the nvidia,tegra20-timer.txt documentation file.
      
      This second version takes into account the following requests from
      Rob Herring <robherring2@gmail.com>:
      
      - Per-IP block patches have been combined into a single patch
      
      - Explicit documentation about which compatible strings are actually
        matched by the driver has been removed.  In its place is implicit
        documentation that loosely follows Rob's prescribed format:
      
        "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
         <chip> is tegra30, tegra132, ..." [...]  "You should attempt to
         document known values of <chip> if you use it"
      Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
      Cc: Alexandre Courbot <gnurou@gmail.com>
      Cc: Dylan Reid <dgreid@chromium.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
      Cc: Jingchang Lu <jingchang.lu@freescale.com>
      Cc: John Crispin <blogic@openwrt.org>
      Cc: Kumar Gala <galak@codeaurora.org>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Mikko Perttunen <mperttunen@nvidia.com>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Pawel Moll <pawel.moll@arm.com>
      Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
      Cc: Peter Hurley <peter@hurleysoftware.com>
      Cc: Sean Paul <seanpaul@chromium.org>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Takashi Iwai <tiwai@suse.de>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: "Terje Bergström" <tbergstrom@nvidia.com>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
      Cc: Wolfram Sang <wsa@the-dreams.de>
      Cc: Zhang Rui <rui.zhang@intel.com>
      Cc: dri-devel@lists.freedesktop.org
      Cc: linux-i2c@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-pci@vger.kernel.org
      Cc: linux-pm@vger.kernel.org
      Cc: linux-pwm@vger.kernel.org
      Cc: linux-tegra@vger.kernel.org
      Acked-by: default avatarEduardo Valentin <edubezval@gmail.com>
      Signed-off-by: default avatarRob Herring <robh@kernel.org>
      193c9d23
  4. 29 Jan, 2015 2 commits
    • Baruch Siach's avatar
      clocksource: devicetree: Document Conexant Digicolor timer binding · 9ff99be7
      Baruch Siach authored
      
      
      The Conexant CX92755 SoC provides 8 32-bit timers as part of its so called
      "Agent Communication" block. Timers can be configures either as free running or
      one shot. Each timer has a dedicated interrupt source in the CX92755 interrupts
      controller. The first timer (Timer A) can also be configured as watchdog.
      
      This commit adds devicetree binding definition of this hardware module. The
      binding defined here should be reusable for other SoCs in the Digicolor series.
      Signed-off-by: default avatarBaruch Siach <baruch@tkos.co.il>
      Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
      9ff99be7
    • Daniel Lezcano's avatar
      clockevents: rockchip: Add rockchip timer for rk3288 · 468b8c4c
      Daniel Lezcano authored
      
      
      The rk3288 board uses the architected timers and these ones are shutdown when
      the cpu is powered down. There is a need of a broadcast timer in this case to
      ensure proper wakeup when the cpus are in sleep mode and a timer expires.
      
      This driver provides the basic timer functionnality as a backup for the local
      timers at sleep time.
      
      The timer belongs to the alive subsystem. It includes two programmables 64 bits
      timer channels but the driver only uses 32bits. It works with two operations
      mode: free running and user defined count.
      
      Programing sequence:
      
      1. Timer initialization:
       * Disable the timer by writing '0' to the CONTROLREG register
       * Program the timer mode by writing the mode to the CONTROLREG register
       * Set the interrupt mask
      
      2. Setting the count value:
       * Load the count value to the registers COUNT0 and COUNT1 (not used).
      
      3. Enable the timer
       * Write '1' to the CONTROLREG register with the mode (free running or user)
      Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
      Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
      468b8c4c
  5. 26 Nov, 2014 1 commit
  6. 26 Oct, 2014 3 commits
  7. 28 Sep, 2014 1 commit
  8. 05 Sep, 2014 3 commits
    • Simon Horman's avatar
      clocksource: sh_tmu: Document r8a7779 binding · fb0eee2f
      Simon Horman authored
      
      
      In general Renesas hardware is not documented to the extent
      where the relationship between IP blocks on different SoCs can be assumed
      although they may appear to operate the same way. Furthermore the
      documentation typically does not specify a version for individual
      IP blocks. For these reasons a convention of using the SoC name in place
      of a version and providing SoC-specific compat strings has been adopted.
      
      Although not universally liked this convention is used in the bindings
      for a number of drivers for Renesas hardware. The purpose of this patch is
      to update the Renesas R-Car Timer Unit (TMU) driver to follow this
      convention.
      Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
      Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
      
      ---
      * I plan to follow up with a patch patch to use the new binding in the
        dtsi files for the r8a7779 SoC.
      commit 471269b790aec03385dc4fb127ed7094ff83c16d
      
      v2
      * Suggestions by Mark Rutland and Sergei Shtylyov
        - Compatible strings should be "one or more" not "one" of those listed
        - Describe the generic binding as covering any MTU2 device
        - Re-order compat strings from most to least specific
      
      v3
      * Suggested by Laurent Pinchart
        - Reword in keeping with a similar though more extensive patch for CMT
      fb0eee2f
    • Simon Horman's avatar
      clocksource: sh_mtu2: Document r7s72100 binding · ffd24a54
      Simon Horman authored
      
      
      In general Renesas hardware is not documented to the extent
      where the relationship between IP blocks on different SoCs can be assumed
      although they may appear to operate the same way. Furthermore the
      documentation typically does not specify a version for individual
      IP blocks. For these reasons a convention of using the SoC name in place
      of a version and providing SoC-specific compat strings has been adopted.
      
      Although not universally liked this convention is used in the bindings
      for a number of drivers for Renesas hardware. The purpose of this patch is
      to update the Renesas R-Car Multi-Function Timer Pulse Unit 2 (MTU2) driver
      to follow this convention.
      Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
      Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
      
      ---
      * I plan to follow up with a patch patch to use the new binding in the
        dtsi files for the r7s72100 SoC.
      
      v2
      * Suggestions by Mark Rutland and Sergei Shtylyov
        - Compatible strings should be "one or more" not "one" of those listed
        - Describe the generic binding as covering any MTU2 device
        - Re-order compat strings from most to least specific
      
      v3
      * Suggested by Laurent Pinchart
        - Reword compat documentation for consistency with a more extensive
          CMT change
      ffd24a54
    • Simon Horman's avatar
      clocksource: sh_cmt: Document SoC specific bindings · 01fe3aaa
      Simon Horman authored
      
      
      In general Renesas hardware is not documented to the extent
      where the relationship between IP blocks on different SoCs can be assumed
      although they may appear to operate the same way. Furthermore the
      documentation typically does not specify a version for individual
      IP blocks. For these reasons a convention of using the SoC name in place
      of a version and providing SoC-specific compat strings has been adopted.
      
      Although not universally liked this convention is used in the bindings for
      a number of drivers for Renesas hardware. The purpose of this patch is to
      update the Renesas R-Car Compare Match Timer (CMT) driver to follow this
      convention.
      Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
      Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
      
      ---
      * I plan to follow up with patches to use these new bindings in the
        dtsi files for the affected SoCs.
      
      v2
      * Reorder compat entries so more-specific entries and their fallbacks
        are grouped with the fallback entry coming last.
      * Explicitly document fallback
      
      v3
      * Avoid circular dependency in documentation of fallback
        behaviour of renesas,cmt-48-gen2
      * Use consistent case for SoC names in compat string descriptions
      01fe3aaa
  9. 23 Jul, 2014 2 commits
  10. 04 Jul, 2014 3 commits
  11. 23 May, 2014 1 commit
  12. 22 Apr, 2014 2 commits
  13. 11 Mar, 2014 2 commits
  14. 20 Dec, 2013 1 commit
  15. 11 Dec, 2013 2 commits
  16. 22 Oct, 2013 1 commit
  17. 02 Sep, 2013 2 commits
  18. 31 Jul, 2013 2 commits
  19. 18 Jul, 2013 1 commit
    • Jonas Jensen's avatar
      ARM: clocksource: Add support for MOXA ART SoCs · 07862c1c
      Jonas Jensen authored
      
      
      This patch adds an clocksource driver for the main timer(s)
      found on MOXA ART SoCs.
      
      The MOXA ART SoC provides three separate timers with individual
      count/load/match registers, two are used here:
      
      TIMER1: clockevents, used to support oneshot and periodic events
      TIMER2: set up as a free running counter, used as clocksource
      
      Timers are preconfigured by bootloader to count down and interrupt
      on match or zero. Count increments every APB clock cycle and is
      automatically reloaded when it reaches zero.
      Signed-off-by: default avatarJonas Jensen <jonas.jensen@gmail.com>
      Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
      07862c1c
  20. 02 Jul, 2013 1 commit
  21. 06 Jun, 2013 1 commit
    • Daniel Tang's avatar
      clocksource: Add TI-Nspire timer support · 77ba83bb
      Daniel Tang authored
      
      
      This patch adds a clocksource/clockevent driver for the timer found on some
      models in the TI-Nspire calculator series. The timer has two 16bit subtimers
      within its memory mapped I/O interface but only the first can generate
      interrupts. The first subtimer is used to generate clockevents but only if an
      interrupt number and register is given.
      
      The interrupt acknowledgement mechanism is a little strange because the
      interrupt mask and acknowledge registers are located in another memory mapped
      I/O peripheral. The address of this register is passed to the driver through
      device tree bindings.
      
      The second subtimer is used as a clocksource because it isn't capable of
      generating an interrupt. This subtimer is always added.
      Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarDaniel Tang <dt.tangr@gmail.com>
      Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
      77ba83bb
  22. 31 May, 2013 1 commit
    • Linus Walleij's avatar
      ARM: u300: device tree support for the timer · 5a5056cc
      Linus Walleij authored
      
      
      This adds device tree support for the U300 timer, by making
      the memory base offset and IRQ dynamically assigned, then
      optionally looking them up from the device tree.
      
      Since the timer needs to be registered before any platform
      devices are created, we will go into the device tree and look
      up the "/timer@c0014000" node and read our base address and
      IRQ from there.
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      5a5056cc
  23. 28 May, 2013 1 commit
  24. 11 Apr, 2013 1 commit
  25. 09 Apr, 2013 1 commit
  26. 08 Apr, 2013 1 commit
    • Maxime Ripard's avatar
      clocksource: sunxi: Rename sunxi to sun4i · 119fd635
      Maxime Ripard authored
      
      
      During the introduction of the Allwinner SoC platforms, sunxi was
      initially meant as a generic name for all the variants of the Allwinner
      SoC.
      
      It was ok at the time of the support of only the A10 and A13 that
      looks pretty much the same, but it's beginning to be troublesome with
      the future addition of the Allwinner A31 (sun6i) that is quite
      different, and would introduce some weird logic, where sunxi would
      actually mean in some case sun4i and sun5i but without sun6i...
      
      Moreover, it makes the compatible strings naming scheme not consistent
      with other architectures, where usually for this kind of compability, we
      just use the oldest SoC name that has this IP, so let's do just this.
      Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
      119fd635